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base repository: m-labs/misoc
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head repository: m-labs/misoc
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compare: 2a1112b912b3
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  • 3 commits
  • 1 file changed
  • 1 contributor

Commits on Apr 1, 2015

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    5113301 View commit details
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Showing with 6 additions and 7 deletions.
  1. +6 −7 misoclib/soc/__init__.py
13 changes: 6 additions & 7 deletions misoclib/soc/__init__.py
Original file line number Diff line number Diff line change
@@ -1,4 +1,3 @@
import os, struct
from operator import itemgetter

from migen.fhdl.std import *
@@ -133,13 +132,13 @@ def add_wb_slave(self, address_decoder, interface):
raise FinalizeError
self._wb_slaves.append((address_decoder, interface))

def check_memory_region(self, name, origin):
def add_memory_region(self, name, origin, length):
def in_this_region(addr):
return addr >= origin and addr < origin + length
for n, o, l in self.memory_regions:
if n == name or o == origin:
if n == name or in_this_region(o) or in_this_region(o+l-1):
raise ValueError("Memory region conflict between {} and {}".format(n, name))

def add_memory_region(self, name, origin, length):
self.check_memory_region(name, origin)
self.memory_regions.append((name, origin, length))

def register_mem(self, name, address, interface, size=None):
@@ -178,9 +177,9 @@ def do_finalize(self):
data_width=self.csr_data_width, address_width=self.csr_address_width)
self.submodules.csrcon = csr.Interconnect(self.wishbone2csr.csr, self.csrbankarray.get_buses())
for name, csrs, mapaddr, rmap in self.csrbankarray.banks:
self.add_csr_region(name, self.mem_map["csr"]+0x80000000+0x800*mapaddr, flen(rmap.bus.dat_w), csrs)
self.add_csr_region(name, self.mem_map["csr"]+0x80000000+0x800*mapaddr, self.csr_data_width, csrs)
for name, memory, mapaddr, mmap in self.csrbankarray.srams:
self.add_csr_region(name, self.mem_map["csr"]+0x80000000+0x800*mapaddr, flen(rmap.bus.dat_w), memory)
self.add_csr_region(name, self.mem_map["csr"]+0x80000000+0x800*mapaddr, self.csr_data_width, memory)

# Interrupts
if hasattr(self.cpu_or_bridge, "interrupt"):