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base repository: m-labs/misoc
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compare: 9137b91e9ed9
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  • 3 commits
  • 5 files changed
  • 1 contributor

Commits on Mar 26, 2015

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    9a9af17 View commit details
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Showing with 9 additions and 20 deletions.
  1. +3 −3 misoclib/mem/sdram/__init__.py
  2. +0 −8 misoclib/mem/sdram/module.py
  3. +5 −7 misoclib/mem/sdram/phy/simphy.py
  4. +1 −1 software/bios/sdram.c
  5. +0 −1 software/bios/sdram.h
6 changes: 3 additions & 3 deletions misoclib/mem/sdram/__init__.py
Original file line number Diff line number Diff line change
@@ -4,8 +4,8 @@
def PhySettings(memtype, dfi_databits, nphases, rdphase, wrphase, rdcmdphase, wrcmdphase, cl, read_latency, write_latency, cwl=0):
return PhySettingsT(memtype, dfi_databits, nphases, rdphase, wrphase, rdcmdphase, wrcmdphase, cl, cwl, read_latency, write_latency)

GeomSettingsT = namedtuple("_GeomSettings", "databits bankbits rowbits colbits addressbits")
def GeomSettings(databits, bankbits, rowbits, colbits):
return GeomSettingsT(databits, bankbits, rowbits, colbits, max(rowbits, colbits))
GeomSettingsT = namedtuple("_GeomSettings", "bankbits rowbits colbits addressbits")
def GeomSettings(bankbits, rowbits, colbits):
return GeomSettingsT(bankbits, rowbits, colbits, max(rowbits, colbits))

TimingSettings = namedtuple("TimingSettings", "tRP tRCD tWR tWTR tREFI tRFC")
8 changes: 0 additions & 8 deletions misoclib/mem/sdram/module.py
Original file line number Diff line number Diff line change
@@ -25,7 +25,6 @@ def __init__(self, clk_freq, memtype, geom_settings, timing_settings):
self.clk_freq = clk_freq
self.memtype = memtype
self.geom_settings = sdram.GeomSettings(
databits=geom_settings["nbits"],
bankbits=log2_int(geom_settings["nbanks"]),
rowbits=log2_int(geom_settings["nrows"]),
colbits=log2_int(geom_settings["ncols"]),
@@ -48,7 +47,6 @@ def ns(self, t, margin=True):
# SDR
class IS42S16160(SDRAMModule):
geom_settings = {
"nbits": 16,
"nbanks": 4,
"nrows": 8192,
"ncols": 512
@@ -68,7 +66,6 @@ def __init__(self, clk_freq):

class MT48LC4M16(SDRAMModule):
geom_settings = {
"nbits": 16,
"nbanks": 4,
"nrows": 4096,
"ncols": 256
@@ -87,7 +84,6 @@ def __init__(self, clk_freq):

class AS4C16M16(SDRAMModule):
geom_settings = {
"nbits": 16,
"nbanks": 4,
"nrows": 8192,
"ncols": 512
@@ -108,7 +104,6 @@ def __init__(self, clk_freq):
# DDR
class MT46V32M16(SDRAMModule):
geom_settings = {
"nbits": 16,
"nbanks": 4,
"nrows": 8192,
"ncols": 1024
@@ -128,7 +123,6 @@ def __init__(self, clk_freq):
# LPDDR
class MT46H32M16(SDRAMModule):
geom_settings = {
"nbits": 16,
"nbanks": 4,
"nrows": 8192,
"ncols": 1024
@@ -148,7 +142,6 @@ def __init__(self, clk_freq):
# DDR2
class MT47H128M8(SDRAMModule):
geom_settings = {
"nbits": 8,
"nbanks": 8,
"nrows": 16384,
"ncols": 1024
@@ -168,7 +161,6 @@ def __init__(self, clk_freq):
# DDR3
class MT8JTF12864(SDRAMModule):
geom_settings = {
"nbits": 8,
"nbanks": 8,
"nrows": 65536,
"ncols": 1024
12 changes: 5 additions & 7 deletions misoclib/mem/sdram/phy/simphy.py
Original file line number Diff line number Diff line change
@@ -87,17 +87,16 @@ def __init__(self, dfi, n):
]

class SDRAMPHYSim(Module):
def __init__(self, module, nmodules=1):
def __init__(self, module, data_width):
addressbits = module.geom_settings.addressbits
databits = module.geom_settings.databits
bankbits = module.geom_settings.bankbits
rowbits = module.geom_settings.rowbits
colbits = module.geom_settings.colbits

# XXX expose this to user
self.settings = sdram.PhySettings(
memtype=module.memtype,
dfi_databits=databits,
dfi_databits=data_width,
nphases=1,
rdphase=0,
wrphase=0,
@@ -109,13 +108,12 @@ def __init__(self, module, nmodules=1):
)
self.module = module

self.dfi = Interface(addressbits, bankbits, databits)
self.dfi = Interface(addressbits, bankbits, data_width)

###
nbanks = 2**bankbits
nrows = 2**rowbits
ncols = 2**colbits
data_width = databits*nmodules

# DFI phases
phases = [DFIPhase(self.dfi, n) for n in range(self.settings.nphases)]
@@ -194,6 +192,6 @@ def __init__(self, module, nmodules=1):
banks_read_data = new_banks_read_data

self.comb += [
Cat(iter([phase.rddata_valid for phase in phases])).eq(banks_read),
Cat(iter([phase.rddata for phase in phases])).eq(banks_read_data)
Cat(*[phase.rddata_valid for phase in phases]).eq(banks_read),
Cat(*[phase.rddata for phase in phases]).eq(banks_read_data)
]
2 changes: 1 addition & 1 deletion software/bios/sdram.c
Original file line number Diff line number Diff line change
@@ -428,7 +428,7 @@ int sdrlevel(void)
#define ONEZERO 0xAAAAAAAA
#define ZEROONE 0x55555555

unsigned int seed_to_data(unsigned int seed, int random)
static unsigned int seed_to_data(unsigned int seed, int random)
{
if (random)
return 1664525*seed + 1013904223;
1 change: 0 additions & 1 deletion software/bios/sdram.h
Original file line number Diff line number Diff line change
@@ -17,7 +17,6 @@ void sdrwloff(void);
int sdrlevel(void);
#endif

unsigned int seed_to_data(unsigned int seed, int random);
int memtest_silent(void);
int memtest(void);
int sdrinit(void);