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base repository: m-labs/migen
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head repository: m-labs/migen
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compare: 21c5fb6f6c01
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  • 3 commits
  • 3 files changed
  • 2 contributors

Commits on Mar 29, 2015

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Showing with 8 additions and 4 deletions.
  1. +5 −1 mibuild/platforms/kc705.py
  2. +2 −2 mibuild/platforms/lx9_microboard.py
  3. +1 −1 mibuild/platforms/usrp_b100.py
6 changes: 5 additions & 1 deletion mibuild/platforms/kc705.py
Original file line number Diff line number Diff line change
@@ -383,7 +383,11 @@ class Platform(XilinxPlatform):
def __init__(self, toolchain="vivado", programmer="xc3sprog"):
XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors,
toolchain=toolchain)
self.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g ConfigRate:12 -g SPI_buswidth:4"
if toolchain == "ise":
self.toolchain.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g ConfigRate:12 -g SPI_buswidth:4"
elif toolchain == "vivado":
self.toolchain.bitstream_commands = ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"]
self.programmer = programmer

def create_programmer(self):
4 changes: 2 additions & 2 deletions mibuild/platforms/lx9_microboard.py
Original file line number Diff line number Diff line change
@@ -110,8 +110,8 @@ def __init__(self):
self.add_platform_command("""
CONFIG VCCAUX = "3.3";
""")
self.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g SPI_buswidth:4"
self.ise_commands = """
self.toolchain.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g SPI_buswidth:4"
self.toolchain.ise_commands = """
promgen -w -spi -c FF -p mcs -o {build_name}.mcs -u 0 {build_name}.bit
"""

2 changes: 1 addition & 1 deletion mibuild/platforms/usrp_b100.py
Original file line number Diff line number Diff line change
@@ -118,7 +118,7 @@ class Platform(XilinxPlatform):

def __init__(self):
XilinxPlatform.__init__(self, "xc3s1400a-ft256-4", _io)
self.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g UnusedPin:PullUp"
self.toolchain.bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -w -g UnusedPin:PullUp"

def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)