m-labs · Mar 28, 2015 · Mar 28, 2015 · Mar 28, 2015
Showing with 65 additions and 75 deletions.

+4 −2 misoclib/mem/sdram/core/lasmicon/__init__.py

+52 −51 misoclib/mem/sdram/core/lasmicon/refresher.py

+3 −4 misoclib/mem/sdram/module.py

+6 −18 misoclib/mem/sdram/phy/simphy.py
diff --git a/misoclib/mem/sdram/core/lasmicon/__init__.py b/misoclib/mem/sdram/core/lasmicon/__init__.py
@@ -11,7 +11,8 @@ def __init__(self, req_queue_size=8,
 			read_time=32, write_time=16,
 			with_l2=True, l2_size=8192,
 			with_bandwidth=False,
-			with_memtest=False):
+			with_memtest=False,
+			with_refresh=True):
 		self.req_queue_size = req_queue_size
 		self.read_time = read_time
 		self.write_time = write_time
@@ -22,6 +23,7 @@ def __init__(self, req_queue_size=8,
 		else:
 			self.with_bandwidth = with_bandwidth
 		self.with_memtest = with_memtest
+		self.with_refresh = with_refresh
 
 class LASMIcon(Module):
 	def __init__(self, phy_settings, geom_settings, timing_settings, controller_settings, **kwargs):
@@ -47,7 +49,7 @@ def __init__(self, phy_settings, geom_settings, timing_settings, controller_sett
 		###
 
 		self.submodules.refresher = Refresher(geom_settings.addressbits, geom_settings.bankbits,
-			timing_settings.tRP, timing_settings.tREFI, timing_settings.tRFC)
+			timing_settings.tRP, timing_settings.tREFI, timing_settings.tRFC, enabled=controller_settings.with_refresh)
 		self.submodules.bank_machines = [BankMachine(geom_settings, timing_settings, controller_settings, address_align, i,
 				getattr(self.lasmic, "bank"+str(i)))
 			for i in range(2**geom_settings.bankbits)]

diff --git a/misoclib/mem/sdram/core/lasmicon/refresher.py b/misoclib/mem/sdram/core/lasmicon/refresher.py
@@ -5,64 +5,65 @@
 from misoclib.mem.sdram.core.lasmicon.multiplexer import *
 
 class Refresher(Module):
-	def __init__(self, a, ba, tRP, tREFI, tRFC):
+	def __init__(self, a, ba, tRP, tREFI, tRFC, enabled=True):
 		self.req = Signal()
 		self.ack = Signal() # 1st command 1 cycle after assertion of ack
 		self.cmd = CommandRequest(a, ba)
 
 		###
 
-		# Refresh sequence generator:
-		# PRECHARGE ALL --(tRP)--> AUTO REFRESH --(tRFC)--> done
-		seq_start = Signal()
-		seq_done = Signal()
-		self.sync += [
-			self.cmd.a.eq(2**10),
-			self.cmd.ba.eq(0),
-			self.cmd.cas_n.eq(1),
-			self.cmd.ras_n.eq(1),
-			self.cmd.we_n.eq(1),
-			seq_done.eq(0)
-		]
-		self.sync += timeline(seq_start, [
-			(1, [
-				self.cmd.ras_n.eq(0),
-				self.cmd.we_n.eq(0)
-			]),
-			(1+tRP, [
-				self.cmd.cas_n.eq(0),
-				self.cmd.ras_n.eq(0)
-			]),
-			(1+tRP+tRFC, [
-				seq_done.eq(1)
+		if enabled:
+			# Refresh sequence generator:
+			# PRECHARGE ALL --(tRP)--> AUTO REFRESH --(tRFC)--> done
+			seq_start = Signal()
+			seq_done = Signal()
+			self.sync += [
+				self.cmd.a.eq(2**10),
+				self.cmd.ba.eq(0),
+				self.cmd.cas_n.eq(1),
+				self.cmd.ras_n.eq(1),
+				self.cmd.we_n.eq(1),
+				seq_done.eq(0)
+			]
+			self.sync += timeline(seq_start, [
+				(1, [
+					self.cmd.ras_n.eq(0),
+					self.cmd.we_n.eq(0)
+				]),
+				(1+tRP, [
+					self.cmd.cas_n.eq(0),
+					self.cmd.ras_n.eq(0)
+				]),
+				(1+tRP+tRFC, [
+					seq_done.eq(1)
+				])
 			])
-		])
 
-		# Periodic refresh counter
-		counter = Signal(max=tREFI)
-		start = Signal()
-		self.sync += [
-			start.eq(0),
-			If(counter == 0,
-				start.eq(1),
-				counter.eq(tREFI - 1)
-			).Else(
-				counter.eq(counter - 1)
-			)
-		]
+			# Periodic refresh counter
+			counter = Signal(max=tREFI)
+			start = Signal()
+			self.sync += [
+				start.eq(0),
+				If(counter == 0,
+					start.eq(1),
+					counter.eq(tREFI - 1)
+				).Else(
+					counter.eq(counter - 1)
+				)
+			]
 
-		# Control FSM
-		fsm = FSM()
-		self.submodules += fsm
-		fsm.act("IDLE", If(start, NextState("WAIT_GRANT")))
-		fsm.act("WAIT_GRANT",
-			self.req.eq(1),
-			If(self.ack,
-				seq_start.eq(1),
-				NextState("WAIT_SEQ")
+			# Control FSM
+			fsm = FSM()
+			self.submodules += fsm
+			fsm.act("IDLE", If(start, NextState("WAIT_GRANT")))
+			fsm.act("WAIT_GRANT",
+				self.req.eq(1),
+				If(self.ack,
+					seq_start.eq(1),
+					NextState("WAIT_SEQ")
+				)
+			)
+			fsm.act("WAIT_SEQ",
+				self.req.eq(1),
+				If(seq_done, NextState("IDLE"))
 			)
-		)
-		fsm.act("WAIT_SEQ",
-			self.req.eq(1),
-			If(seq_done, NextState("IDLE"))
-		)
diff --git a/misoclib/mem/sdram/module.py b/misoclib/mem/sdram/module.py
@@ -13,7 +13,6 @@
 #      configurations.
 #    - Modules can have different speedgrades, add support for it (and also add
 #      a check to verify clk_freq is in the supported range)
-#   Try to uniformize tREFI computations between modules
 
 from math import ceil
 
@@ -57,7 +56,7 @@ class IS42S16160(SDRAMModule):
 		"tRCD":		20,
 		"tWR":		20,
 		"tWTR":		2,
-		"tREFI":	7800,
+		"tREFI":	64*1000*1000/8192,
 		"tRFC":		70
 	}
 	def __init__(self, clk_freq):
@@ -94,7 +93,7 @@ class AS4C16M16(SDRAMModule):
 		"tRCD":		18,
 		"tWR":		12,
 		"tWTR":		2,
-		"tREFI":	7800,
+		"tREFI":	64*1000*1000/8192,
 		"tRFC":		60
 	}
 	def __init__(self, clk_freq):
@@ -113,7 +112,7 @@ class MT46V32M16(SDRAMModule):
 		"tRCD":		15,
 		"tWR":		15,
 		"tWTR":		2,
-		"tREFI":	7800,
+		"tREFI":	64*1000*1000/8192,
 		"tRFC":		70
 	}
 	def __init__(self, clk_freq):

diff --git a/misoclib/mem/sdram/phy/simphy.py b/misoclib/mem/sdram/phy/simphy.py
@@ -3,10 +3,9 @@
 
 # SDRAM simulation PHY at DFI level
 # Status:
-# - tested against software memtest with SDR with Verilator.
+# - tested against software memtest with SDR/DDR/LPDDR/DDR2 with Verilator.
 # TODO:
-# - expose phy_settings to user
-# - test with DDR, LPDDR, DDR2 and DDR3
+# - test with DDR3
 # - add $display support to Migen and manage timing violations?
 
 from migen.fhdl.std import *
@@ -87,33 +86,22 @@ def __init__(self, dfi, n):
 		]
 
 class SDRAMPHYSim(Module):
-	def __init__(self, module, data_width):
+	def __init__(self, module, settings):
 		addressbits = module.geom_settings.addressbits
 		bankbits = module.geom_settings.bankbits
 		rowbits = module.geom_settings.rowbits
 		colbits = module.geom_settings.colbits
 
-		# XXX expose this to user
-		self.settings = sdram.PhySettings(
-			memtype=module.memtype,
-			dfi_databits=data_width,
-			nphases=1,
-			rdphase=0,
-			wrphase=0,
-			rdcmdphase=0,
-			wrcmdphase=0,
-			cl=2,
-			read_latency=4,
-			write_latency=0
-		)
+		self.settings = settings
 		self.module = module
 
-		self.dfi = Interface(addressbits, bankbits, data_width)
+		self.dfi = Interface(addressbits, bankbits, self.settings.dfi_databits, self.settings.nphases)
 
 		###
 		nbanks = 2**bankbits
 		nrows = 2**rowbits
 		ncols = 2**colbits
+		data_width = self.settings.dfi_databits*self.settings.nphases
 
 		# DFI phases
 		phases = [DFIPhase(self.dfi, n) for n in range(self.settings.nphases)]