sdram/phy/simphy: OK with DDR3

enjoy-digital · enjoy-digital · commit 75ee8a5db926 · 2015-03-28T01:59:55.000+01:00
diff --git a/misoclib/mem/sdram/phy/simphy.py b/misoclib/mem/sdram/phy/simphy.py
@@ -2,10 +2,8 @@
 # License: BSD
 
 # SDRAM simulation PHY at DFI level
-# Status:
-# - tested against software memtest with SDR/DDR/LPDDR/DDR2 with Verilator.
+# tested with SDR/DDR/DDR2/LPDDR/DDR3
 # TODO:
-# - test with DDR3
 # - add $display support to Migen and manage timing violations?
 
 from migen.fhdl.std import *
