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base repository: m-labs/misoc
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compare: 369086a178e6
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  • 2 commits
  • 11 files changed
  • 1 contributor

Commits on Apr 1, 2015

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    273242b View commit details
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    369086a View commit details
Showing with 48 additions and 71 deletions.
  1. +3 −3 make.py
  2. +18 −24 misoclib/soc/__init__.py
  3. +1 −2 misoclib/soc/sdram.py
  4. +2 −6 targets/de0nano.py
  5. +9 −12 targets/kc705.py
  6. +2 −4 targets/minispartan6.py
  7. +2 −2 targets/mlabs_video.py
  8. +4 −8 targets/pipistrello.py
  9. +4 −7 targets/ppro.py
  10. +2 −2 targets/simple.py
  11. +1 −1 targets/versa.py
6 changes: 3 additions & 3 deletions make.py
Original file line number Diff line number Diff line change
@@ -125,9 +125,9 @@ def _get_args():
actions["build-bios"] = True
if not actions["load-bitstream"]:
actions["flash-bitstream"] = True
if not soc.with_integrated_rom:
if not soc.integrated_rom_size:
actions["flash-bios"] = True
if actions["build-bitstream"] and soc.with_integrated_rom:
if actions["build-bitstream"] and soc.integrated_rom_size:
actions["build-bios"] = True
if actions["build-bios"]:
actions["build-headers"] = True
@@ -176,7 +176,7 @@ def _get_args():
raise OSError("BIOS build failed")

if actions["build-bitstream"]:
if soc.with_integrated_rom:
if soc.integrated_rom_size:
with open(bios_file, "rb") as boot_file:
boot_data = []
while True:
42 changes: 18 additions & 24 deletions misoclib/soc/__init__.py
Original file line number Diff line number Diff line change
@@ -34,9 +34,9 @@ class SoC(Module):
}
def __init__(self, platform, clk_freq,
cpu_type="lm32", cpu_reset_address=0x00000000,
with_integrated_rom=False, rom_size=0x8000,
with_integrated_sram=True, sram_size=4096,
with_integrated_main_ram=False, main_ram_size=64*1024,
integrated_rom_size=0,
integrated_sram_size=4096,
integrated_main_ram_size=0,
with_csr=True, csr_data_width=8, csr_address_width=14,
with_uart=True, uart_baudrate=115200,
with_identifier=True,
@@ -45,19 +45,13 @@ def __init__(self, platform, clk_freq,
self.clk_freq = clk_freq

self.cpu_type = cpu_type
if with_integrated_rom:
self.cpu_reset_address = 0
else:
self.cpu_reset_address = cpu_reset_address
if integrated_rom_size:
cpu_reset_address = 0
self.cpu_reset_address = cpu_reset_address

self.with_integrated_rom = with_integrated_rom
self.rom_size = rom_size

self.with_integrated_sram = with_integrated_sram
self.sram_size = sram_size

self.with_integrated_main_ram = with_integrated_main_ram
self.main_ram_size = main_ram_size
self.integrated_rom_size = integrated_rom_size
self.integrated_sram_size = integrated_sram_size
self.integrated_main_ram_size = integrated_main_ram_size

self.with_uart = with_uart
self.uart_baudrate = uart_baudrate
@@ -84,18 +78,18 @@ def __init__(self, platform, clk_freq,
self.add_wb_master(self.cpu_or_bridge.ibus)
self.add_wb_master(self.cpu_or_bridge.dbus)

if with_integrated_rom:
self.submodules.rom = wishbone.SRAM(rom_size, read_only=True)
self.register_rom(self.rom.bus, rom_size)
if integrated_rom_size:
self.submodules.rom = wishbone.SRAM(integrated_rom_size, read_only=True)
self.register_rom(self.rom.bus, integrated_rom_size)

if with_integrated_sram:
self.submodules.sram = wishbone.SRAM(sram_size)
self.register_mem("sram", self.mem_map["sram"], self.sram.bus, sram_size)
if integrated_sram_size:
self.submodules.sram = wishbone.SRAM(integrated_sram_size)
self.register_mem("sram", self.mem_map["sram"], self.sram.bus, integrated_sram_size)

# Note: Main Ram can be used when no external SDRAM is available and use SDRAM mapping.
if with_integrated_main_ram:
self.submodules.main_ram = wishbone.SRAM(main_ram_size)
self.register_mem("main_ram", self.mem_map["main_ram"], self.main_ram.bus, main_ram_size)
if integrated_main_ram_size:
self.submodules.main_ram = wishbone.SRAM(integrated_main_ram_size)
self.register_mem("main_ram", self.mem_map["main_ram"], self.main_ram.bus, integrated_main_ram_size)

if with_csr:
self.submodules.wishbone2csr = wishbone2csr.WB2CSR(bus_csr=csr.Interface(csr_data_width, csr_address_width))
3 changes: 1 addition & 2 deletions misoclib/soc/sdram.py
Original file line number Diff line number Diff line change
@@ -64,7 +64,6 @@ def register_sdram_phy(self, phy):
self.submodules.wishbone2lasmi = FullMemoryWE(wishbone2lasmi.WB2LASMI(l2_size//4, self.sdram.crossbar.get_master()))
else:
self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(l2_size//4, self.sdram.crossbar.get_master())
lasmic = self.sdram.controller.lasmic
self.register_mem("main_ram", self.mem_map["main_ram"], self.wishbone2lasmi.wishbone, main_ram_size)

# MINICON frontend
@@ -79,7 +78,7 @@ def register_sdram_phy(self, phy):
raise NotImplementedError("Unsupported SDRAM width of {} > 32".format(sdram_width))

def do_finalize(self):
if not self.with_integrated_main_ram:
if not self.integrated_ram_size:
if not self._sdram_phy_registered:
raise FinalizeError("Need to call SDRAMSoC.register_sdram_phy()")
SoC.do_finalize(self)
8 changes: 2 additions & 6 deletions targets/de0nano.py
Original file line number Diff line number Diff line change
@@ -1,12 +1,8 @@
from migen.fhdl.std import *
from migen.bus import wishbone

from misoclib.cpu.peripherals import gpio
from misoclib.mem import sdram
from misoclib.mem.sdram.module import IS42S16160
from misoclib.mem.sdram.phy import gensdrphy
from misoclib.mem.sdram.core.lasmicon import LASMIconSettings
from misoclib.com import uart
from misoclib.soc.sdram import SDRAMSoC

class _PLL(Module):
@@ -86,13 +82,13 @@ class BaseSoC(SDRAMSoC):
def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
SDRAMSoC.__init__(self, platform,
clk_freq=100*1000000,
with_integrated_rom=True,
integrated_rom_size=0x8000,
sdram_controller_settings=sdram_controller_settings,
**kwargs)

self.submodules.crg = _CRG(platform)

if not self.with_integrated_main_ram:
if not self.integrated_main_ram_size:
self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"), IS42S16160(self.clk_freq))
self.register_sdram_phy(self.sdrphy)

21 changes: 9 additions & 12 deletions targets/kc705.py
Original file line number Diff line number Diff line change
@@ -1,7 +1,6 @@
from migen.fhdl.std import *
from migen.genlib.resetsync import AsyncResetSynchronizer

from misoclib.mem import sdram
from misoclib.mem.sdram.module import MT8JTF12864
from misoclib.mem.sdram.phy import k7ddrphy
from misoclib.mem.sdram.core.lasmicon import LASMIconSettings
@@ -85,20 +84,18 @@ def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwa

self.submodules.crg = _CRG(platform)

if not self.with_integrated_main_ram:
if not self.integrated_main_ram_size:
self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"), MT8JTF12864(self.clk_freq))
self.register_sdram_phy(self.ddrphy)

spiflash_pads = platform.request("spiflash")
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
self.submodules.spiflash = spiflash.SpiFlash(spiflash_pads, dummy=11, div=2)
self.flash_boot_address = 0xb00000

# If not in ROM, BIOS is in SPI flash
if not self.with_integrated_rom:
if not self.integrated_rom_size:
spiflash_pads = platform.request("spiflash")
spiflash_pads.clk = Signal()
self.specials += Instance("STARTUPE2",
i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
self.submodules.spiflash = spiflash.SpiFlash(spiflash_pads, dummy=11, div=2)
self.flash_boot_address = 0xb00000
self.register_rom(self.spiflash.bus)

class MiniSoC(BaseSoC):
6 changes: 2 additions & 4 deletions targets/minispartan6.py
Original file line number Diff line number Diff line change
@@ -3,11 +3,9 @@
from migen.fhdl.std import *
from migen.genlib.resetsync import AsyncResetSynchronizer

from misoclib.mem import sdram
from misoclib.mem.sdram.module import AS4C16M16
from misoclib.mem.sdram.phy import gensdrphy
from misoclib.mem.sdram.core.lasmicon import LASMIconSettings
from misoclib.mem.flash import spiflash
from misoclib.soc.sdram import SDRAMSoC

class _CRG(Module):
@@ -66,13 +64,13 @@ class BaseSoC(SDRAMSoC):
def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
clk_freq = 80*1000000
SDRAMSoC.__init__(self, platform, clk_freq,
with_integrated_rom=True,
integrated_rom_size=0x8000,
sdram_controller_settings=sdram_controller_settings,
**kwargs)

self.submodules.crg = _CRG(platform, clk_freq)

if not self.with_integrated_main_ram:
if not self.integrated_main_ram_size:
self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"), AS4C16M16(clk_freq))
self.register_sdram_phy(self.sdrphy)

4 changes: 2 additions & 2 deletions targets/mlabs_video.py
Original file line number Diff line number Diff line change
@@ -44,7 +44,7 @@ def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwa

self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq)

if not self.with_integrated_main_ram:
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), MT46V32M16(self.clk_freq),
rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1")
self.register_sdram_phy(self.ddrphy)
@@ -53,7 +53,7 @@ def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwa
self.ddrphy.clk4x_rd_strb.eq(self.crg.clk4x_rd_strb)
]

if not self.with_integrated_rom:
if not self.integrated_rom_size:
clk_period_ns = 1000000000/self.clk_freq
self.submodules.norflash = norflash16.NorFlash16(platform.request("norflash"),
ceil(110/clk_period_ns), ceil(50/clk_period_ns))
12 changes: 4 additions & 8 deletions targets/pipistrello.py
Original file line number Diff line number Diff line change
@@ -3,7 +3,6 @@
from migen.fhdl.std import *
from migen.genlib.resetsync import AsyncResetSynchronizer

from misoclib.mem import sdram
from misoclib.mem.sdram.module import MT46H32M16
from misoclib.mem.sdram.phy import s6ddrphy
from misoclib.mem.sdram.core.lasmicon import LASMIconSettings
@@ -97,16 +96,14 @@ class BaseSoC(SDRAMSoC):

def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
clk_freq = 75*1000000
if not kwargs.get("with_integrated_rom"):
kwargs["rom_size"] = 0x1000000 # 128 Mb
SDRAMSoC.__init__(self, platform, clk_freq,
cpu_reset_address=0x170000, # 1.5 MB
sdram_controller_settings=sdram_controller_settings,
**kwargs)

self.submodules.crg = _CRG(platform, clk_freq)

if not self.with_integrated_main_ram:
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), MT46H32M16(self.clk_freq),
rd_bitslip=1, wr_bitslip=3, dqs_ddr_alignment="C1")
self.comb += [
@@ -118,10 +115,9 @@ def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwa
""")
self.register_sdram_phy(self.ddrphy)

self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash4x"), dummy=10, div=4)
# If not in ROM, BIOS is in SPI flash
if not self.with_integrated_rom:
if not self.integrated_rom_size:
self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash4x"), dummy=10, div=4)
self.flash_boot_address = 0x180000
self.register_rom(self.spiflash.bus)
self.register_rom(self.spiflash.bus, 0x1000000)

default_subtarget = BaseSoC
11 changes: 4 additions & 7 deletions targets/ppro.py
Original file line number Diff line number Diff line change
@@ -3,7 +3,6 @@
from migen.fhdl.std import *
from migen.genlib.resetsync import AsyncResetSynchronizer

from misoclib.mem import sdram
from misoclib.mem.sdram.module import MT48LC4M16
from misoclib.mem.sdram.phy import gensdrphy
from misoclib.mem.sdram.core.lasmicon import LASMIconSettings
@@ -77,15 +76,13 @@ def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwa

self.submodules.crg = _CRG(platform, clk_freq)

if not self.with_integrated_main_ram:
if not self.integrated_main_ram_size:
self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"), MT48LC4M16(clk_freq))
self.register_sdram_phy(self.sdrphy)

self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), dummy=4, div=6)
self.flash_boot_address = 0x70000

# If not in ROM, BIOS is in SPI flash
if not self.with_integrated_rom:
if not self.integrated_rom_size:
self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), dummy=4, div=6)
self.flash_boot_address = 0x70000
self.register_rom(self.spiflash.bus)

default_subtarget = BaseSoC
4 changes: 2 additions & 2 deletions targets/simple.py
Original file line number Diff line number Diff line change
@@ -10,8 +10,8 @@ class BaseSoC(SoC):
def __init__(self, platform, **kwargs):
SoC.__init__(self, platform,
clk_freq=int((1/(platform.default_clk_period))*1000000000),
with_integrated_rom=True,
with_integrated_main_ram=True, main_ram_size=16*1024,
integrated_rom_size=0x8000,
integrated_main_ram_size=16*1024,
**kwargs)
self.submodules.crg = CRG(platform.request(platform.default_clk_name))

2 changes: 1 addition & 1 deletion targets/versa.py
Original file line number Diff line number Diff line change
@@ -9,7 +9,7 @@ class BaseSoC(SoC):
def __init__(self, platform, **kwargs):
SoC.__init__(self, platform,
clk_freq=100*1000000,
with_integrated_rom=True,
integrated_rom_size=0x8000,
**kwargs)
self.submodules.crg = CRG(platform.request("clk100"), ~platform.request("rst_n"))
self.comb += platform.request("user_led", 0).eq(ResetSignal())