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  • 2 commits
  • 21 files changed
  • 1 contributor

Commits on Mar 25, 2015

  1. sdram: use names that are more explicit for bank_a, row_a,...: bankbi… 

    …ts, rowbits, .... Add databits to GeomSettings.
    @enjoy-digital
    enjoy-digital committed Mar 25, 2015
    7
    Copy the full SHA
    7ea9e2b View commit details

  2. sdram: pass module as phy parameter, define memtype in modules and on… 

    …ly keep phy parameter in register_sdram_phy
    @enjoy-digital
    enjoy-digital committed Mar 25, 2015
    Copy the full SHA
    ba8b24d View commit details
12 changes: 6 additions & 6 deletions misoclib/mem/sdram/__init__.py
View file
Original file line number Diff line number Diff line change
@@ -1,11 +1,11 @@
from collections import namedtuple

PhySettingsT = namedtuple("PhySettings", "memtype dfi_d nphases rdphase wrphase rdcmdphase wrcmdphase cl cwl read_latency write_latency")
def PhySettings(memtype, dfi_d, nphases, rdphase, wrphase, rdcmdphase, wrcmdphase, cl, read_latency, write_latency, cwl=0):
return PhySettingsT(memtype, dfi_d, nphases, rdphase, wrphase, rdcmdphase, wrcmdphase, cl, cwl, read_latency, write_latency)
PhySettingsT = namedtuple("PhySettings", "memtype dfi_databits nphases rdphase wrphase rdcmdphase wrcmdphase cl cwl read_latency write_latency")
def PhySettings(memtype, dfi_databits, nphases, rdphase, wrphase, rdcmdphase, wrcmdphase, cl, read_latency, write_latency, cwl=0):
return PhySettingsT(memtype, dfi_databits, nphases, rdphase, wrphase, rdcmdphase, wrcmdphase, cl, cwl, read_latency, write_latency)

GeomSettingsT = namedtuple("_GeomSettings", "bank_a row_a col_a mux_a")
def GeomSettings(bank_a, row_a, col_a):
return GeomSettingsT(bank_a, row_a, col_a, max(row_a, col_a))
GeomSettingsT = namedtuple("_GeomSettings", "databits bankbits rowbits colbits addressbits")
def GeomSettings(databits, bankbits, rowbits, colbits):
return GeomSettingsT(databits, bankbits, rowbits, colbits, max(rowbits, colbits))

TimingSettings = namedtuple("TimingSettings", "tRP tRCD tWR tWTR tREFI tRFC")
4 changes: 2 additions & 2 deletions misoclib/mem/sdram/core/__init__.py
View file
Original file line number Diff line number Diff line change
@@ -9,8 +9,8 @@
class SDRAMCore(Module, AutoCSR):
def __init__(self, phy, geom_settings, timing_settings, controller_settings, **kwargs):
# DFI
self.submodules.dfii = dfii.DFIInjector(geom_settings.mux_a, geom_settings.bank_a,
phy.settings.dfi_d, phy.settings.nphases)
self.submodules.dfii = dfii.DFIInjector(geom_settings.addressbits, geom_settings.bankbits,
phy.settings.dfi_databits, phy.settings.nphases)
self.comb += Record.connect(self.dfii.master, phy.dfi)

# LASMICON
18 changes: 9 additions & 9 deletions misoclib/mem/sdram/core/lasmicon/__init__.py
View file
Original file line number Diff line number Diff line change
@@ -28,26 +28,26 @@ def __init__(self, phy_settings, geom_settings, timing_settings, controller_sett
burst_length = phy_settings.nphases*2 # command multiplication*DDR
address_align = log2_int(burst_length)

self.dfi = dfi.Interface(geom_settings.mux_a,
geom_settings.bank_a,
phy_settings.dfi_d,
self.dfi = dfi.Interface(geom_settings.addressbits,
geom_settings.bankbits,
phy_settings.dfi_databits,
phy_settings.nphases)
self.lasmic = lasmibus.Interface(
aw=geom_settings.row_a + geom_settings.col_a - address_align,
dw=phy_settings.dfi_d*phy_settings.nphases,
nbanks=2**geom_settings.bank_a,
aw=geom_settings.rowbits + geom_settings.colbits - address_align,
dw=phy_settings.dfi_databits*phy_settings.nphases,
nbanks=2**geom_settings.bankbits,
req_queue_size=controller_settings.req_queue_size,
read_latency=phy_settings.read_latency+1,
write_latency=phy_settings.write_latency+1)
self.nrowbits = geom_settings.col_a - address_align
self.nrowbits = geom_settings.colbits - address_align

###

self.submodules.refresher = Refresher(geom_settings.mux_a, geom_settings.bank_a,
self.submodules.refresher = Refresher(geom_settings.addressbits, geom_settings.bankbits,
timing_settings.tRP, timing_settings.tREFI, timing_settings.tRFC)
self.submodules.bank_machines = [BankMachine(geom_settings, timing_settings, controller_settings, address_align, i,
getattr(self.lasmic, "bank"+str(i)))
for i in range(2**geom_settings.bank_a)]
for i in range(2**geom_settings.bankbits)]
self.submodules.multiplexer = Multiplexer(phy_settings, geom_settings, timing_settings, controller_settings,
self.bank_machines, self.refresher,
self.dfi, self.lasmic,
14 changes: 7 additions & 7 deletions misoclib/mem/sdram/core/lasmicon/bankmachine.py
View file
Original file line number Diff line number Diff line change
@@ -7,19 +7,19 @@
from misoclib.mem.sdram.core.lasmicon.multiplexer import *

class _AddressSlicer:
def __init__(self, col_a, address_align):
self.col_a = col_a
def __init__(self, colbits, address_align):
self.colbits = colbits
self.address_align = address_align

def row(self, address):
split = self.col_a - self.address_align
split = self.colbits - self.address_align
if isinstance(address, int):
return address >> split
else:
return address[split:]

def col(self, address):
split = self.col_a - self.address_align
split = self.colbits - self.address_align
if isinstance(address, int):
return (address & (2**split - 1)) << self.address_align
else:
@@ -29,7 +29,7 @@ class BankMachine(Module):
def __init__(self, geom_settings, timing_settings, controller_settings, address_align, bankn, req):
self.refresh_req = Signal()
self.refresh_gnt = Signal()
self.cmd = CommandRequestRW(geom_settings.mux_a, geom_settings.bank_a)
self.cmd = CommandRequestRW(geom_settings.addressbits, geom_settings.bankbits)

###

@@ -46,11 +46,11 @@ def __init__(self, geom_settings, timing_settings, controller_settings, address_
]
reqf = self.req_fifo.dout

slicer = _AddressSlicer(geom_settings.col_a, address_align)
slicer = _AddressSlicer(geom_settings.colbits, address_align)

# Row tracking
has_openrow = Signal()
openrow = Signal(geom_settings.row_a)
openrow = Signal(geom_settings.rowbits)
hit = Signal()
self.comb += hit.eq(openrow == slicer.row(reqf.adr))
track_open = Signal()
2 changes: 1 addition & 1 deletion misoclib/mem/sdram/core/lasmicon/multiplexer.py
View file
Original file line number Diff line number Diff line change
@@ -108,7 +108,7 @@ def __init__(self, phy_settings, geom_settings, timing_settings, controller_sett
]

# Command steering
nop = CommandRequest(geom_settings.mux_a, geom_settings.bank_a)
nop = CommandRequest(geom_settings.addressbits, geom_settings.bankbits)
commands = [nop, choose_cmd.cmd, choose_req.cmd, refresher.cmd] # nop must be 1st
(STEER_NOP, STEER_CMD, STEER_REQ, STEER_REFRESH) = range(4)
steerer = _Steerer(commands, dfi)
32 changes: 16 additions & 16 deletions misoclib/mem/sdram/core/minicon/__init__.py
View file
Original file line number Diff line number Diff line change
@@ -5,30 +5,30 @@
from misoclib.mem.sdram.phy import dfi as dfibus

class _AddressSlicer:
def __init__(self, col_a, bank_a, row_a, address_align):
self.col_a = col_a
self.bank_a = bank_a
self.row_a = row_a
self.max_a = col_a + row_a + bank_a
def __init__(self, colbits, bankbits, rowbits, address_align):
self.colbits = colbits
self.bankbits = bankbits
self.rowbits = rowbits
self.max_a = colbits + rowbits + bankbits
self.address_align = address_align

def row(self, address):
split = self.bank_a + self.col_a
split = self.bankbits + self.colbits
if isinstance(address, int):
return address >> split
else:
return address[split:self.max_a]

def bank(self, address):
mask = 2**(self.bank_a + self.col_a) - 1
shift = self.col_a
mask = 2**(self.bankbits + self.colbits) - 1
shift = self.colbits
if isinstance(address, int):
return (address & mask) >> shift
else:
return address[self.col_a:self.col_a+self.bank_a]
return address[self.colbits:self.colbits+self.bankbits]

def col(self, address):
split = self.col_a
split = self.colbits
if isinstance(address, int):
return (address & (2**split - 1)) << self.address_align
else:
@@ -46,20 +46,20 @@ def __init__(self, phy_settings, geom_settings, timing_settings):
burst_length = phy_settings.nphases*2 # command multiplication*DDR
address_align = log2_int(burst_length)

nbanks = range(2**geom_settings.bank_a)
nbanks = range(2**geom_settings.bankbits)
A10_ENABLED = 0
COLUMN = 1
ROW = 2
rdphase = phy_settings.rdphase
wrphase = phy_settings.wrphase

self.dfi = dfi = dfibus.Interface(geom_settings.mux_a,
geom_settings.bank_a,
phy_settings.dfi_d,
self.dfi = dfi = dfibus.Interface(geom_settings.addressbits,
geom_settings.bankbits,
phy_settings.dfi_databits,
phy_settings.nphases)

self.bus = bus = wishbone.Interface(data_width=phy_settings.nphases*flen(dfi.phases[rdphase].rddata))
slicer = _AddressSlicer(geom_settings.col_a, geom_settings.bank_a, geom_settings.row_a, address_align)
slicer = _AddressSlicer(geom_settings.colbits, geom_settings.bankbits, geom_settings.rowbits, address_align)
refresh_req = Signal()
refresh_ack = Signal()
refresh_counter = Signal(max=timing_settings.tREFI+1)
@@ -70,7 +70,7 @@ def __init__(self, phy_settings, geom_settings, timing_settings):
has_curbank_openrow = Signal()

# Extra bit means row is active when asserted
self.openrow = openrow = Array(Signal(geom_settings.row_a + 1) for b in nbanks)
self.openrow = openrow = Array(Signal(geom_settings.rowbits + 1) for b in nbanks)

self.comb += [
hit.eq(openrow[slicer.bank(bus.adr)] == Cat(slicer.row(bus.adr), 1)),
31 changes: 20 additions & 11 deletions misoclib/mem/sdram/module.py
View file
Original file line number Diff line number Diff line change
@@ -21,12 +21,14 @@
from misoclib.mem import sdram

class SDRAMModule:
def __init__(self, clk_freq, geom_settings, timing_settings):
def __init__(self, clk_freq, memtype, geom_settings, timing_settings):
self.clk_freq = clk_freq
self.memtype = memtype
self.geom_settings = sdram.GeomSettings(
bank_a=log2_int(geom_settings["nbanks"]),
row_a=log2_int(geom_settings["nrows"]),
col_a=log2_int(geom_settings["ncols"])
databits=geom_settings["nbits"],
bankbits=log2_int(geom_settings["nbanks"]),
rowbits=log2_int(geom_settings["nrows"]),
colbits=log2_int(geom_settings["ncols"]),
)
self.timing_settings = sdram.TimingSettings(
tRP=self.ns(timing_settings["tRP"]),
@@ -46,6 +48,7 @@ def ns(self, t, margin=True):
# SDR
class IS42S16160(SDRAMModule):
geom_settings = {
"nbits": 16,
"nbanks": 4,
"nrows": 8192,
"ncols": 512
@@ -60,11 +63,12 @@ class IS42S16160(SDRAMModule):
"tRFC": 70
}
def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, self.geom_settings,
SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings,
self.timing_settings)

class MT48LC4M16(SDRAMModule):
geom_settings = {
"nbits": 16,
"nbanks": 4,
"nrows": 4096,
"ncols": 256
@@ -78,11 +82,12 @@ class MT48LC4M16(SDRAMModule):
"tRFC": 66
}
def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, self.geom_settings,
SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings,
self.timing_settings)

class AS4C16M16(SDRAMModule):
geom_settings = {
"nbits": 16,
"nbanks": 4,
"nrows": 8192,
"ncols": 512
@@ -97,12 +102,13 @@ class AS4C16M16(SDRAMModule):
"tRFC": 60
}
def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, self.geom_settings,
SDRAMModule.__init__(self, clk_freq, "SDR", self.geom_settings,
self.timing_settings)

# DDR
class MT46V32M16(SDRAMModule):
geom_settings = {
"nbits": 16,
"nbanks": 4,
"nrows": 8192,
"ncols": 1024
@@ -116,12 +122,13 @@ class MT46V32M16(SDRAMModule):
"tRFC": 70
}
def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, self.geom_settings,
SDRAMModule.__init__(self, clk_freq, "DDR", self.geom_settings,
self.timing_settings)

# LPDDR
class MT46H32M16(SDRAMModule):
geom_settings = {
"nbits": 16,
"nbanks": 4,
"nrows": 8192,
"ncols": 1024
@@ -135,12 +142,13 @@ class MT46H32M16(SDRAMModule):
"tRFC": 72
}
def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, self.geom_settings,
SDRAMModule.__init__(self, clk_freq, "LPDDR", self.geom_settings,
self.timing_settings)

# DDR2
class MT47H128M8(SDRAMModule):
geom_settings = {
"nbits": 8,
"nbanks": 8,
"nrows": 16384,
"ncols": 1024
@@ -154,12 +162,13 @@ class MT47H128M8(SDRAMModule):
"tRFC": 127.5
}
def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, self.geom_settings,
SDRAMModule.__init__(self, clk_freq, "DDR2", self.geom_settings,
self.timing_settings)

# DDR3
class MT8JTF12864(SDRAMModule):
geom_settings = {
"nbits": 8,
"nbanks": 8,
"nrows": 65536,
"ncols": 1024
@@ -173,5 +182,5 @@ class MT8JTF12864(SDRAMModule):
"tRFC": 70
}
def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, self.geom_settings,
SDRAMModule.__init__(self, clk_freq, "DDR3", self.geom_settings,
self.timing_settings)
48 changes: 24 additions & 24 deletions misoclib/mem/sdram/phy/dfi.py
View file
Original file line number Diff line number Diff line change
@@ -1,42 +1,42 @@
from migen.fhdl.std import *
from migen.genlib.record import *

def phase_cmd_description(a, ba):
def phase_cmd_description(addressbits, bankbits):
return [
("address", a, DIR_M_TO_S),
("bank", ba, DIR_M_TO_S),
("cas_n", 1, DIR_M_TO_S),
("cs_n", 1, DIR_M_TO_S),
("ras_n", 1, DIR_M_TO_S),
("we_n", 1, DIR_M_TO_S),
("cke", 1, DIR_M_TO_S),
("odt", 1, DIR_M_TO_S),
("reset_n", 1, DIR_M_TO_S)
("address", addressbits, DIR_M_TO_S),
("bank", bankbits, DIR_M_TO_S),
("cas_n", 1, DIR_M_TO_S),
("cs_n", 1, DIR_M_TO_S),
("ras_n", 1, DIR_M_TO_S),
("we_n", 1, DIR_M_TO_S),
("cke", 1, DIR_M_TO_S),
("odt", 1, DIR_M_TO_S),
("reset_n", 1, DIR_M_TO_S)
]

def phase_wrdata_description(d):
def phase_wrdata_description(databits):
return [
("wrdata", d, DIR_M_TO_S),
("wrdata_en", 1, DIR_M_TO_S),
("wrdata_mask", d//8, DIR_M_TO_S)
("wrdata", databits, DIR_M_TO_S),
("wrdata_en", 1, DIR_M_TO_S),
("wrdata_mask", databits//8, DIR_M_TO_S)
]

def phase_rddata_description(d):
def phase_rddata_description(databits):
return [
("rddata_en", 1, DIR_M_TO_S),
("rddata", d, DIR_S_TO_M),
("rddata_valid", 1, DIR_S_TO_M)
("rddata_en", 1, DIR_M_TO_S),
("rddata", databits, DIR_S_TO_M),
("rddata_valid", 1, DIR_S_TO_M)
]

def phase_description(a, ba, d):
r = phase_cmd_description(a, ba)
r += phase_wrdata_description(d)
r += phase_rddata_description(d)
def phase_description(addressbits, bankbits, databits):
r = phase_cmd_description(addressbits, bankbits)
r += phase_wrdata_description(databits)
r += phase_rddata_description(databits)
return r

class Interface(Record):
def __init__(self, a, ba, d, nphases=1):
layout = [("p"+str(i), phase_description(a, ba, d)) for i in range(nphases)]
def __init__(self, addressbits, bankbits, databits, nphases=1):
layout = [("p"+str(i), phase_description(addressbits, bankbits, databits)) for i in range(nphases)]
Record.__init__(self, layout)
self.phases = [getattr(self, "p"+str(i)) for i in range(nphases)]
for p in self.phases:
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