m-labs · Mar 30, 2015 · Mar 30, 2015 · Mar 30, 2015 · Mar 30, 2015
Showing with 96 additions and 119 deletions.

+5 −5 mibuild/generic_platform.py

+16 −32 migen/fhdl/edif.py

+20 −20 migen/fhdl/specials.py

+39 −59 migen/fhdl/verilog.py

+2 −3 migen/sim/generic.py

+14 −0 tools/xilinx_strace_tailor.sh
diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py
@@ -268,17 +268,17 @@ def resolve_signals(self, vns):
 	def _get_source(self, fragment, gen_fn):
 		if not isinstance(fragment, _Fragment):
 			fragment = fragment.get_fragment()
-		# generate source and namespace
-		convert = gen_fn(fragment)
-		return str(convert), convert.ns
+		# generate source
+		src, vns = gen_fn(fragment)
+		return src, vns
 
 	def get_verilog(self, fragment, **kwargs):
 		return self._get_source(fragment, lambda f: verilog.convert(f, self.constraint_manager.get_io_signals(),
-				create_clock_domains=False, **kwargs))
+				return_ns=True, create_clock_domains=False, **kwargs))
 
 	def get_edif(self, fragment, cell_library, vendor, device, **kwargs):
 		return self._get_source(fragment, lambda f: edif.convert(f, self.constraint_manager.get_io_signals(),
-				cell_library, vendor, device, **kwargs))
+				cell_library, vendor, device, return_ns=True, **kwargs))
 
 	def build(self, fragment):
 		raise NotImplementedError("GenericPlatform.build must be overloaded")

diff --git a/migen/fhdl/edif.py b/migen/fhdl/edif.py
@@ -182,36 +182,20 @@ def _generate_connections(f, ios, ns):
 		r[io].append(_NetBranch(portname=io, instancename=""))
 	return r
 
-class EDIFConvert:
-	def __init__(self, f, ios, cell_library, vendor, device, name="top"):
-		self.cell_library
-		self.vendor = vendor
-		self.device = device
-		self.name = name
-
-		if not isinstance(f, _Fragment):
-			f = f.get_fragment()
-		if f.comb != [] or f.sync != {}:
-			raise ValueError("Edif conversion can only handle synthesized fragments")
-		if ios is None:
-			ios = set()
-		cells = _generate_cells(f)
-		ns = build_namespace(list_special_ios(f, True, True, True))
-		instances = _generate_instances(f, ns)
-		inouts = _generate_ios(f, ios, ns)
-		connections = _generate_connections(f, ios, ns)
-
-		self.f = f
-		self.ios = ios
-		self.cells = cells
-		self.ns = ns
-		self.instances = instances
-		self.inouts = inouts
-		self.connections = connections
-
-	def __str__(self):
-		return _write_edif(self.cells, self.inouts, self.instances, self.connections,
-			self.cell_library, self.name, self.device, self.vendor)
-
 def convert(f, ios, cell_library, vendor, device, name="top", return_ns=False):
-	return EDIFConvert(f, ios, cell_library, vendor, device, name, return_ns)
+	if not isinstance(f, _Fragment):
+		f = f.get_fragment()
+	if f.comb != [] or f.sync != {}:
+		raise ValueError("Edif conversion can only handle synthesized fragments")
+	if ios is None:
+		ios = set()
+	cells = _generate_cells(f)
+	ns = build_namespace(list_special_ios(f, True, True, True))
+	instances = _generate_instances(f, ns)
+	inouts = _generate_ios(f, ios, ns)
+	connections = _generate_connections(f, ios, ns)
+	r =  _write_edif(cells, inouts, instances, connections, cell_library, name, device, vendor)
+	if return_ns:
+		return r, ns
+	else:
+		return r
diff --git a/migen/fhdl/specials.py b/migen/fhdl/specials.py
@@ -6,15 +6,6 @@
 from migen.fhdl.tracer import get_obj_var_name
 from migen.fhdl.verilog import _printexpr as verilog_printexpr
 
-def _new_file(fdict, requested_filename, contents):
-	filename = requested_filename
-	i = 1
-	while filename in fdict.keys():
-		filename = requested_filename + str(i)
-		i += 1
-	fdict[filename] = contents
-	return filename, fdict
-
 class Special(HUID):
 	def iter_expressions(self):
 		for x in []:
@@ -57,7 +48,7 @@ def iter_expressions(self):
 			yield self, attr, target_context
 
 	@staticmethod
-	def emit_verilog(tristate, ns, fdict):
+	def emit_verilog(tristate, ns):
 		def pe(e):
 			return verilog_printexpr(ns, e)[0]
 		w, s = value_bits_sign(tristate.target)
@@ -67,7 +58,7 @@ def pe(e):
 		if tristate.i is not None:
 			r += "assign " + pe(tristate.i) + " = " + pe(tristate.target) + ";\n"
 		r += "\n"
-		return r, fdict
+		return r
 
 class TSTriple:
 	def __init__(self, bits_sign=None, min=None, max=None, reset_o=0, reset_oe=0):
@@ -132,7 +123,7 @@ def iter_expressions(self):
 				yield item, "expr", SPECIAL_INOUT
 
 	@staticmethod
-	def emit_verilog(instance, ns, fdict):
+	def emit_verilog(instance, ns):
 		r = instance.of + " "
 		parameters = list(filter(lambda i: isinstance(i, Instance.Parameter), instance.items))
 		if parameters:
@@ -174,7 +165,7 @@ def emit_verilog(instance, ns, fdict):
 			r += ")" + synthesis_directive + ";\n\n"
 		else:
 			r += ");\n\n"
-		return r, fdict
+		return r
 
 (READ_FIRST, WRITE_FIRST, NO_CHANGE) = range(3)
 
@@ -207,8 +198,8 @@ def iter_expressions(self):
 			yield self, attr, target_context
 
 	@staticmethod
-	def emit_verilog(port, ns, fdict):
-		return "", fdict # done by parent Memory object
+	def emit_verilog(port, ns):
+		return "" # done by parent Memory object
 
 class Memory(Special):
 	def __init__(self, width, depth, init=None, name=None):
@@ -246,7 +237,7 @@ def get_port(self, write_capable=False, async_read=False,
 		return mp
 
 	@staticmethod
-	def emit_verilog(memory, ns, fdict):
+	def emit_verilog(memory, ns):
 		r = ""
 		def gn(e):
 			if isinstance(e, Memory):
@@ -316,12 +307,21 @@ def gn(e):
 		r += "\n"
 
 		if memory.init is not None:
-			memory_filename, fdict = _new_file(fdict, gn(memory) + ".init", memory.init)
+			memory_filename = gn(memory) + ".init"
+
+			# XXX move I/O to mibuild?
+			# (Implies mem init won't work with simple Migen examples?)
+			f = open(memory_filename, "w")
+			for d in memory.init:
+				f.write("{:x}\n".format(d))
+			f.close()
+
 			r += "initial begin\n"
 			r += "$readmemh(\"" + memory_filename + "\", " + gn(memory) + ");\n"
 			r += "end\n\n"
 
-		return r, fdict
+
+		return r
 
 class SynthesisDirective(Special):
 	def __init__(self, template, **signals):
@@ -330,7 +330,7 @@ def __init__(self, template, **signals):
 		self.signals = signals
 
 	@staticmethod
-	def emit_verilog(directive, ns, fdict):
+	def emit_verilog(directive, ns):
 		name_dict = dict((k, ns.get_name(sig)) for k, sig in directive.signals.items())
 		formatted = directive.template.format(**name_dict)
-		return "// synthesis " + formatted + "\n", fdict
+		return "// synthesis " + formatted + "\n"
diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
@@ -1,6 +1,5 @@
 from functools import partial
 from operator import itemgetter
-from collections import OrderedDict
 
 from migen.fhdl.structure import *
 from migen.fhdl.structure import _Operator, _Slice, _Assign, _Fragment
@@ -258,73 +257,54 @@ def _lower_specials(overrides, specials):
 		f.specials -= lowered_specials2
 	return f, lowered_specials
 
-def _printspecials(overrides, specials, ns, fdict):
+def _printspecials(overrides, specials, ns):
 	r = ""
 	for special in sorted(specials, key=lambda x: x.huid):
-		pr, fdict = _call_special_classmethod(overrides, special, "emit_verilog", ns, fdict)
+		pr = _call_special_classmethod(overrides, special, "emit_verilog", ns)
 		if pr is None:
 			raise NotImplementedError("Special " + str(special) + " failed to implement emit_verilog")
 		r += pr
-	return r, fdict
-
-class VerilogConvert:
-	def __init__(self, f, ios=None, name="top",
-  			special_overrides=dict(),
-  			create_clock_domains=True,
-  			display_run=False):
-		self.name = name
-		self.special_overrides = special_overrides
-		self.display_run = display_run
+	return r
 
-		if not isinstance(f, _Fragment):
-			f = f.get_fragment()
-		if ios is None:
-			ios = set()
+def convert(f, ios=None, name="top",
+  return_ns=False,
+  special_overrides=dict(),
+  create_clock_domains=True,
+  display_run=False):
+	if not isinstance(f, _Fragment):
+		f = f.get_fragment()
+	if ios is None:
+		ios = set()
 
-		for cd_name in list_clock_domains(f):
-			try:
-				f.clock_domains[cd_name]
-			except KeyError:
-				if create_clock_domains:
-					cd = ClockDomain(cd_name)
-					f.clock_domains.append(cd)
-					ios |= {cd.clk, cd.rst}
-				else:
-					raise KeyError("Unresolved clock domain: '"+cd_name+"'")
+	for cd_name in list_clock_domains(f):
+		try:
+			f.clock_domains[cd_name]
+		except KeyError:
+			if create_clock_domains:
+				cd = ClockDomain(cd_name)
+				f.clock_domains.append(cd)
+				ios |= {cd.clk, cd.rst}
+			else:
+				raise KeyError("Unresolved clock domain: '"+cd_name+"'")
 
-		f = lower_complex_slices(f)
-		insert_resets(f)
-		f = lower_basics(f)
-		fs, lowered_specials = _lower_specials(special_overrides, f.specials)
-		f += lower_basics(fs)
+	f = lower_complex_slices(f)
+	insert_resets(f)
+	f = lower_basics(f)
+	fs, lowered_specials = _lower_specials(special_overrides, f.specials)
+	f += lower_basics(fs)
 
-		ns = build_namespace(list_signals(f) \
-			| list_special_ios(f, True, True, True) \
-			| ios)
+	ns = build_namespace(list_signals(f) \
+		| list_special_ios(f, True, True, True) \
+		| ios)
 
-		self.f = f
-		self.ios = ios
-		self.ns = ns
-		self.lowered_specials = lowered_specials
+	r = "/* Machine-generated using Migen */\n"
+	r += _printheader(f, ios, name, ns)
+	r += _printcomb(f, ns, display_run)
+	r += _printsync(f, ns)
+	r += _printspecials(special_overrides, f.specials - lowered_specials, ns)
+	r += "endmodule\n"
 
-	def __str__(self):
-		r = "/* Machine-generated using Migen */\n"
-		r += _printheader(self.f, self.ios, self.name, self.ns)
-		r += _printcomb(self.f, self.ns, self.display_run)
-		r += _printsync(self.f, self.ns)
-		fdict = OrderedDict()
-		src, fdict = _printspecials(self.special_overrides, self.f.specials - self.lowered_specials, self.ns, fdict)
-		r += src
-		for filename, contents in fdict.items():
-			f = open(filename, "w")
-			for data in contents:
-				f.write("{:x}\n".format(data))
-			f.close()
-		r += "endmodule\n"
+	if return_ns:
+		return r, ns
+	else:
 		return r
-
-def convert(f, ios=None, name="top",
-  special_overrides=dict(),
-  create_clock_domains=True,
-  display_run=False):
-	return VerilogConvert(f, ios, name, special_overrides, create_clock_domains, display_run)
diff --git a/migen/sim/generic.py b/migen/sim/generic.py
@@ -87,17 +87,16 @@ def __init__(self, fragment, top_level=None, sim_runner=None, sockaddr="simsocke
 		c_top = self.top_level.get(sockaddr)
 
 		fragment = fragment + _Fragment(clock_domains=top_level.clock_domains)
-		verilog_convert = verilog.convert(fragment,
+		c_fragment, self.namespace = verilog.convert(fragment,
 			ios=self.top_level.ios,
 			name=self.top_level.dut_type,
 			return_ns=True,
 			**vopts)
-		c_dut, self.namespace = str(verilog_convert), verilog_convert.ns
 
 		self.cycle_counter = -1
 
 		self.sim_runner = sim_runner
-		self.sim_runner.start(c_top, c_dut)
+		self.sim_runner.start(c_top, c_fragment)
 		self.ipc.accept()
 		reply = self.ipc.recv()
 		assert(isinstance(reply, MessageTick))

diff --git a/tools/xilinx_strace_tailor.sh b/tools/xilinx_strace_tailor.sh
@@ -0,0 +1,14 @@
+#!/bin/sh
+# Copyright Robert Jordens <robert@joerdens.org> 2014,2015
+
+# assuming your xilinx toolchain lives in /opt/Xilinx,
+# run `strace-tailor.sh [synthesis script] [options]`
+# then in your current directory, `opt/Xilinx/*` is the
+# minimal toolchain required for this synthesis script run.
+
+PREFIX=\\/opt\\/Xilinx\\/
+
+strace -e trace=file,process -f -o strace.log $@
+sed -n "s/^.*\"\\(${PREFIX}[^\"]*\\)\".*$/\\1/p" strace.log \
+	| sort | uniq | tr '\n' '\0' \
+	| xargs -0 cp --parent --no-dereference --preserve=all -t .