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base repository: m-labs/migen
base: 15e24b6c1061
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head repository: m-labs/migen
compare: b469571afe8a
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  • 4 commits
  • 6 files changed
  • 1 contributor

Commits on Mar 30, 2015

  1. Revert "migen/fhdl/specials: use fdict to pass memory initialization … 

    …files to VerilogConvert and print them in __str__ method"

This reverts commit 95cfc44.
    @sbourdeauducq
    sbourdeauducq committed Mar 30, 2015
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  2. Revert "migen/fhdl: pass fdict filename --> contents to specials" 

    This reverts commit ea04947.
    @sbourdeauducq
    sbourdeauducq committed Mar 30, 2015
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  3. Revert "migen: create VerilogConvert and EDIFConvert classes and retu… 

    …rn it with convert functions"

This reverts commit f03aa76.
    @sbourdeauducq
    sbourdeauducq committed Mar 30, 2015
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  4. move xilinx_strace_tailor to tools

    @sbourdeauducq
    sbourdeauducq committed Mar 30, 2015
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