Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: m-labs/misoc
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: f4c35e358efd
Choose a base ref
...
head repository: m-labs/misoc
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: 54a88da5b8dd
Choose a head ref
  • 2 commits
  • 1 file changed
  • 2 contributors

Commits on Mar 27, 2015

  1. pipistrello: add por reset counter 

    * this is a temporary fix that should be removed once the
combination of bitstream-in-flash, mor1kx, bios-in-flash works
    @jordens @sbourdeauducq
    jordens authored and sbourdeauducq committed Mar 27, 2015
    Copy the full SHA
    54c14c7 View commit details

  2. Merge branch 'master' of https://github.com/m-labs/misoc

    @sbourdeauducq
    sbourdeauducq committed Mar 27, 2015
    Copy the full SHA
    54a88da View commit details
Showing with 6 additions and 1 deletion.
  1. +6 −1 targets/pipistrello.py
7 changes: 6 additions & 1 deletion targets/pipistrello.py
View file
Original file line number Diff line number Diff line change
@@ -58,7 +58,12 @@ def __init__(self, platform, clk_freq):
)
self.specials += Instance("BUFG", i_I=pll[5], o_O=self.cd_sys.clk)
reset = platform.request("user_btn")
self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_lckd | reset)
self.clock_domains.cd_por = ClockDomain()
por = Signal(max=1 << 11, reset=(1 << 11) - 1)
self.sync.por += If(por != 0, por.eq(por - 1))
self.comb += self.cd_por.clk.eq(self.cd_sys.clk)
self.specials += AsyncResetSynchronizer(self.cd_por, reset)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_lckd | (por > 0))
self.specials += Instance("BUFG", i_I=pll[2], o_O=self.cd_sdram_half.clk)
self.specials += Instance("BUFPLL", p_DIVIDE=4,
i_PLLIN=pll[0], i_GCLK=self.cd_sys.clk,