sdram: remove redundant with_l2 parameter (equivalent to l2_size != 0)

m-labs · Mar 29, 2015 · b313772 · b313772
1 parent be20fba
commit b313772
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Showing 2 changed files with 3 additions and 4 deletions.
diff --git a/misoclib/mem/sdram/core/lasmicon/__init__.py b/misoclib/mem/sdram/core/lasmicon/__init__.py
@@ -9,14 +9,13 @@
 class LASMIconSettings:
 	def __init__(self, req_queue_size=8,
 			read_time=32, write_time=16,
-			with_l2=True, l2_size=8192,
+			l2_size=8192,
 			with_bandwidth=False,
 			with_memtest=False,
 			with_refresh=True):
 		self.req_queue_size = req_queue_size
 		self.read_time = read_time
 		self.write_time = write_time
-		self.with_l2 = with_l2
 		self.l2_size = l2_size
 		if with_memtest:
 			self.with_bandwidth = True

diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py
@@ -53,8 +53,8 @@ def register_sdram_phy(self, phy):
 				self.submodules.memtest_w = memtest.MemtestWriter(self.sdram.crossbar.get_master())
 				self.submodules.memtest_r = memtest.MemtestReader(self.sdram.crossbar.get_master())
 
-			if self.sdram_controller_settings.with_l2:
-				l2_size = self.sdram_controller_settings.l2_size
+			l2_size = self.sdram_controller_settings.l2_size
+			if l2_size != 0:
 				# XXX Vivado 2014.X workaround, Vivado is not able to map correctly our L2 cache.
 				# Issue is reported to Xilinx and should be fixed in next releases (2015.1?).
 				# Remove this workaround when fixed by Xilinx.