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Commit b313772

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committedMar 29, 2015
sdram: remove redundant with_l2 parameter (equivalent to l2_size != 0)
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2 files changed

+3
-4
lines changed

2 files changed

+3
-4
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‎misoclib/mem/sdram/core/lasmicon/__init__.py

+1-2
Original file line numberDiff line numberDiff line change
@@ -9,14 +9,13 @@
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class LASMIconSettings:
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def __init__(self, req_queue_size=8,
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read_time=32, write_time=16,
12-
with_l2=True, l2_size=8192,
12+
l2_size=8192,
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with_bandwidth=False,
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with_memtest=False,
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with_refresh=True):
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self.req_queue_size = req_queue_size
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self.read_time = read_time
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self.write_time = write_time
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self.with_l2 = with_l2
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self.l2_size = l2_size
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if with_memtest:
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self.with_bandwidth = True

‎misoclib/soc/sdram.py

+2-2
Original file line numberDiff line numberDiff line change
@@ -53,8 +53,8 @@ def register_sdram_phy(self, phy):
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self.submodules.memtest_w = memtest.MemtestWriter(self.sdram.crossbar.get_master())
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self.submodules.memtest_r = memtest.MemtestReader(self.sdram.crossbar.get_master())
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if self.sdram_controller_settings.with_l2:
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l2_size = self.sdram_controller_settings.l2_size
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l2_size = self.sdram_controller_settings.l2_size
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if l2_size != 0:
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# XXX Vivado 2014.X workaround, Vivado is not able to map correctly our L2 cache.
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# Issue is reported to Xilinx and should be fixed in next releases (2015.1?).
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# Remove this workaround when fixed by Xilinx.

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