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base repository: m-labs/migen
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head repository: m-labs/migen
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compare: fef08e8c7045
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Apr 11, 2014

  1. mibuild/altera_quartus: set top_level_entity

    @enjoy-digital @sbourdeauducq
    enjoy-digital authored and sbourdeauducq committed Apr 11, 2014
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    82e4980 View commit details

  2. mibuild: add bitstream_ext parameter to platforms

    @enjoy-digital @sbourdeauducq
    enjoy-digital authored and sbourdeauducq committed Apr 11, 2014
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    fef08e8 View commit details
Showing with 3 additions and 0 deletions.
  1. +2 −0 mibuild/altera_quartus.py
  2. +1 −0 mibuild/xilinx_ise.py
2 changes: 2 additions & 0 deletions mibuild/altera_quartus.py
View file
Original file line number Diff line number Diff line change
@@ -45,6 +45,7 @@ def _build_qsf(named_sc, named_pc):
r += _format_qsf(sig, pins[0], others, resname)
if named_pc:
r += "\n" + "\n\n".join(named_pc)
r += "set_global_assignment -name top_level_entity top\n"
return r

def _build_files(device, sources, vincpaths, named_sc, named_pc, build_name):
@@ -76,6 +77,7 @@ def _run_quartus(build_name, quartus_path):
raise OSError("Subprocess failed")

class AlteraQuartusPlatform(GenericPlatform):
bitstream_ext = ".sof"
def build(self, fragment, build_dir="build", build_name="top",
quartus_path="/opt/Altera", run=True):
tools.mkdir_noerror(build_dir)
1 change: 1 addition & 0 deletions mibuild/xilinx_ise.py
View file
Original file line number Diff line number Diff line change
@@ -184,6 +184,7 @@ def lower(dr):
return XilinxMultiRegImpl(dr.i, dr.o, dr.odomain, dr.n)

class XilinxISEPlatform(GenericPlatform):
bitstream_ext = ".bit"
xst_opt = """-ifmt MIXED
-opt_mode SPEED
-reduce_control_sets auto