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base repository: m-labs/misoc
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head repository: m-labs/misoc
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compare: ec465959d0f5
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  • 2 commits
  • 1 file changed
  • 1 contributor

Commits on Mar 19, 2015

  1. Copy the full SHA
    a10875a View commit details
  2. pipistrello: add user reset

    apparently needed for flashed bitstream, xiped bios, mor1kx
    jordens authored and sbourdeauducq committed Mar 19, 2015
    Copy the full SHA
    ec46595 View commit details
Showing with 6 additions and 6 deletions.
  1. +6 −6 targets/pipistrello.py
12 changes: 6 additions & 6 deletions targets/pipistrello.py
Original file line number Diff line number Diff line change
@@ -55,7 +55,8 @@ def __init__(self, platform, clk_freq):
p_CLKOUT5_PHASE=0., p_CLKOUT5_DIVIDE=p//1, # sys
)
self.specials += Instance("BUFG", i_I=pll[5], o_O=self.cd_sys.clk)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_lckd)
reset = platform.request("user_btn")
self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_lckd | reset)
self.specials += Instance("BUFG", i_I=pll[2], o_O=self.cd_sdram_half.clk)
self.specials += Instance("BUFPLL", p_DIVIDE=4,
i_PLLIN=pll[0], i_GCLK=self.cd_sys.clk,
@@ -67,7 +68,7 @@ def __init__(self, platform, clk_freq):
]
clk_sdram_half_shifted = Signal()
self.specials += Instance("BUFG", i_I=pll[3], o_O=clk_sdram_half_shifted)
clk = platform.request("sdram_clock")
clk = platform.request("ddram_clock")
self.specials += Instance("ODDR2", p_DDR_ALIGNMENT="NONE",
p_INIT=0, p_SRTYPE="SYNC",
i_D0=1, i_D1=0, i_S=0, i_R=0, i_CE=1,
@@ -113,7 +114,7 @@ def __init__(self, platform, **kwargs):
read_time=32,
write_time=16
)
self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("sdram"),
self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"),
"LPDDR", rd_bitslip=1, wr_bitslip=3, dqs_ddr_alignment="C1")
self.comb += [
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
@@ -124,11 +125,10 @@ def __init__(self, platform, **kwargs):
""")
self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing)

self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash4x"), dummy=11, div=2)
self.flash_boot_address = 0x180000

self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash4x"), dummy=10, div=4)
# If not in ROM, BIOS is in SPI flash
if not self.with_rom:
self.flash_boot_address = 0x180000
self.register_rom(self.spiflash.bus)

default_subtarget = BaseSoC