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base repository: m-labs/migen
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head repository: m-labs/migen
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compare: 4fe888702d94
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  • 3 commits
  • 1 file changed
  • 1 contributor

Commits on Mar 19, 2015

  1. pipistrello: rename sdram->ddram

    jordens authored and sbourdeauducq committed Mar 19, 2015
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    860b72c View commit details
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    47ea451 View commit details
  3. pipistrello: switch is a button

    jordens authored and sbourdeauducq committed Mar 19, 2015
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    4fe8887 View commit details
Showing with 4 additions and 3 deletions.
  1. +4 −3 mibuild/platforms/pipistrello.py
7 changes: 4 additions & 3 deletions mibuild/platforms/pipistrello.py
Original file line number Diff line number Diff line change
@@ -9,7 +9,7 @@
("user_led", 3, Pins("A15"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # red at msd
("user_led", 4, Pins("A12"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # red at usb

("user_switch", 0, Pins("N14"), IOStandard("LVTTL"), Misc("PULLDOWN")),
("user_btn", 0, Pins("N14"), IOStandard("LVTTL"), Misc("PULLDOWN")),

("clk50", 0, Pins("H17"), IOStandard("LVTTL")),

@@ -97,13 +97,13 @@
IOStandard("LVTTL")
),

("sdram_clock", 0,
("ddram_clock", 0,
Subsignal("p", Pins("G3")),
Subsignal("n", Pins("G1")),
IOStandard("MOBILE_DDR")
),

("sdram", 0,
("ddram", 0,
Subsignal("a", Pins("J7 J6 H5 L7 F3 H4 H3 H6 D2 D1 F4 D3 G6")),
Subsignal("ba", Pins("F2 F1")),
Subsignal("cke", Pins("H7")),
@@ -130,6 +130,7 @@ class Platform(XilinxPlatform):

def __init__(self):
XilinxPlatform.__init__(self, "xc6slx45-csg324-2", _io, _connectors)
self.toolchain.bitgen_opt += " -g Compress -g ConfigRate:6"

def create_programmer(self):
return XC3SProg("papilio", "bscan_spi_lx45_csg324.bit")