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enjoy-digitalenjoy-digital
committedMar 22, 2015
platforms/minispartan6: fix IOStandard/Slew, add FpgaProg programmer, change default clock to 32MHz
·
0.9.20.1
1 parent 7440ccd commit 200979f

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-35
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+43
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‎mibuild/platforms/minispartan6.py

+43-35
Original file line numberDiff line numberDiff line change
@@ -4,51 +4,51 @@
44
from mibuild.generic_platform import *
55
from mibuild.crg import SimpleCRG
66
from mibuild.xilinx import XilinxPlatform
7-
from mibuild.xilinx.programmer import XC3SProg
7+
from mibuild.xilinx.programmer import XC3SProg, FpgaProg
88

99
_io = [
10-
("user_led", 0, Pins("P11"), IOStandard("LVTTL"), Misc("SLEW=SLOW")),
11-
("user_led", 1, Pins("N9"), IOStandard("LVTTL"), Misc("SLEW=SLOW")),
12-
("user_led", 2, Pins("M9"), IOStandard("LVTTL"), Misc("SLEW=SLOW")),
13-
("user_led", 3, Pins("P9"), IOStandard("LVTTL"), Misc("SLEW=SLOW")),
14-
("user_led", 4, Pins("T8"), IOStandard("LVTTL"), Misc("SLEW=SLOW")),
15-
("user_led", 5, Pins("N8"), IOStandard("LVTTL"), Misc("SLEW=SLOW")),
16-
("user_led", 6, Pins("P8"), IOStandard("LVTTL"), Misc("SLEW=SLOW")),
17-
("user_led", 7, Pins("P7"), IOStandard("LVTTL"), Misc("SLEW=SLOW")),
18-
19-
("user_sw", 0, Pins("L1"), IOStandard("LVTTL"), Misc("PULLUP")),
20-
("user_sw", 1, Pins("L3"), IOStandard("LVTTL"), Misc("PULLUP")),
21-
("user_sw", 2, Pins("L4"), IOStandard("LVTTL"), Misc("PULLUP")),
22-
("user_sw", 3, Pins("L5"), IOStandard("LVTTL"), Misc("PULLUP")),
10+
("user_led", 0, Pins("P11"), IOStandard("LVCMOS33")),
11+
("user_led", 1, Pins("N9"), IOStandard("LVCMOS33")),
12+
("user_led", 2, Pins("M9"), IOStandard("LVCMOS33")),
13+
("user_led", 3, Pins("P9"), IOStandard("LVCMOS33")),
14+
("user_led", 4, Pins("T8"), IOStandard("LVCMOS33")),
15+
("user_led", 5, Pins("N8"), IOStandard("LVCMOS33")),
16+
("user_led", 6, Pins("P8"), IOStandard("LVCMOS33")),
17+
("user_led", 7, Pins("P7"), IOStandard("LVCMOS33")),
18+
19+
("user_sw", 0, Pins("L1"), IOStandard("LVCMOS33"), Misc("PULLUP")),
20+
("user_sw", 1, Pins("L3"), IOStandard("LVCMOS33"), Misc("PULLUP")),
21+
("user_sw", 2, Pins("L4"), IOStandard("LVCMOS33"), Misc("PULLUP")),
22+
("user_sw", 3, Pins("L5"), IOStandard("LVCMOS33"), Misc("PULLUP")),
2323

2424
("clk32", 0, Pins("J4"), IOStandard("LVCMOS33")),
2525
("clk50", 0, Pins("K3"), IOStandard("LVCMOS33")),
2626

2727
("spiflash", 0,
28-
Subsignal("cs_n", Pins("T3"), IOStandard("LVTTL")),
29-
Subsignal("clk", Pins("R11"), IOStandard("LVTTL")),
30-
Subsignal("mosi", Pins("T10"), IOStandard("LVTTL")),
31-
Subsignal("miso", Pins("P10"), IOStandard("LVTTL"))
28+
Subsignal("cs_n", Pins("T3"), IOStandard("LVCMOS33")),
29+
Subsignal("clk", Pins("R11"), IOStandard("LVCMOS33")),
30+
Subsignal("mosi", Pins("T10"), IOStandard("LVCMOS33")),
31+
Subsignal("miso", Pins("P10"), IOStandard("LVCMOS33"))
3232
),
3333

3434
("adc", 0,
35-
Subsignal("cs_n", Pins("F6"), IOStandard("LVTTL")),
36-
Subsignal("clk", Pins("G6"), IOStandard("LVTTL")),
37-
Subsignal("mosi", Pins("H4"), IOStandard("LVTTL")),
38-
Subsignal("miso", Pins("H5"), IOStandard("LVTTL"))
35+
Subsignal("cs_n", Pins("F6"), IOStandard("LVCMOS33")),
36+
Subsignal("clk", Pins("G6"), IOStandard("LVCMOS33")),
37+
Subsignal("mosi", Pins("H4"), IOStandard("LVCMOS33")),
38+
Subsignal("miso", Pins("H5"), IOStandard("LVCMOS33"))
3939
),
4040

4141
("serial", 0,
42-
Subsignal("tx", Pins("N6"), IOStandard("LVTTL")), # FTDI D1
43-
Subsignal("rx", Pins("M7"), IOStandard("LVTTL")) # FTDI D0
42+
Subsignal("tx", Pins("N6"), IOStandard("LVCMOS33")), # FTDI D1
43+
Subsignal("rx", Pins("M7"), IOStandard("LVCMOS33")) # FTDI D0
4444
),
4545

4646
("audio", 0,
47-
Subsignal("a0", Pins("B8"), IOStandard("LVTTL")),
48-
Subsignal("a1", Pins("A8"), IOStandard("LVTTL"))
47+
Subsignal("a0", Pins("B8"), IOStandard("LVCMOS33")),
48+
Subsignal("a1", Pins("A8"), IOStandard("LVCMOS33"))
4949
),
5050

51-
("sdram_clock", 0, Pins("G16"), IOStandard("LVTTL")),
51+
("sdram_clock", 0, Pins("G16"), IOStandard("LVCMOS33"), Misc("SLEW=FAST")),
5252
("sdram", 0,
5353
Subsignal("a", Pins("T15 R16 P15 P16 N16 M15 M16 L16 K15 K16 R15 J16 H15")),
5454
Subsignal("dq", Pins("T13 T12 R12 T9 R9 T7 R7 T6 F16 E15 E16 D16 B16 B15 C16 C15")),
@@ -58,7 +58,8 @@
5858
Subsignal("cs_n", Pins("R1")),
5959
Subsignal("cke", Pins("H16")),
6060
Subsignal("ba", Pins("R14 T14")),
61-
Subsignal("dm", Pins("T5 F15"))
61+
Subsignal("dm", Pins("T5 F15")),
62+
IOStandard("LVCMOS33"), Misc("SLEW=FAST")
6263
),
6364

6465
("sd", 0,
@@ -67,16 +68,17 @@
6768
Subsignal("d", Pins("M10")),
6869
Subsignal("d1", Pins("L10")),
6970
Subsignal("d2", Pins("J11")),
70-
Subsignal("cmd", Pins("K11"))
71+
Subsignal("cmd", Pins("K11")),
72+
IOStandard("LVCMOS33")
7173
),
7274

7375
("dvi_in", 0,
7476
Subsignal("clk_p", Pins("C9"), IOStandard("TMDS_33")),
7577
Subsignal("clk_n", Pins("A9"), IOStandard("TMDS_33")),
7678
Subsignal("data_p", Pins("C7 B6 B5"), IOStandard("TMDS_33")),
7779
Subsignal("data_n", Pins("A7 A6 A5"), IOStandard("TMDS_33")),
78-
Subsignal("scl", Pins("C1"), IOStandard("LVTTL")),
79-
Subsignal("sda", Pins("B1"), IOStandard("LVTTL"))
80+
Subsignal("scl", Pins("C1"), IOStandard("LVCMOS33")),
81+
Subsignal("sda", Pins("B1"), IOStandard("LVCMOS33"))
8082
),
8183

8284
("dvi_out", 0,
@@ -97,11 +99,17 @@
9799
]
98100

99101
class Platform(XilinxPlatform):
100-
default_clk_name = "clk50"
101-
default_clk_period = 20
102+
default_clk_name = "clk32"
103+
default_clk_period = 31.25
102104

103-
def __init__(self, device="xc6slx9"):
105+
def __init__(self, device="xc6slx9", programmer="xc3sprog"):
106+
self.programmer = programmer
104107
XilinxPlatform.__init__(self, device+"-3-ftg256", _io, _connectors)
105108

106109
def create_programmer(self):
107-
return XC3SProg("minispartan6", "bscan_spi_minispartan6.bit")
110+
if self.programmer == "xc3sprog":
111+
return XC3SProg("minispartan6", "bscan_spi_minispartan6.bit")
112+
elif self.programmer == "fpgaprog":
113+
return FpgaProg()
114+
else:
115+
raise ValueError("{} programmer is not supported".format(programmer))

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