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base repository: m-labs/migen
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head repository: m-labs/migen
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compare: 9adf3f02f230
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Mar 16, 2015

  1. fhdl/verilog: do not use initial begin in _printinit (not accepted by…

    … all synthesis tools ex: Synplify Pro does not accept it)
    enjoy-digital committed Mar 16, 2015
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    e946f6e View commit details
  2. fhdl/verilog: add simulation parameter to avoid simulation tricks in …

    …synthetizable code
    
    it's generally better to have identical code between simulations and synthesis, but here tricks inserted for simulation are clearly expected to be simplified by synthesis tools, so it's better not inserting them.
    enjoy-digital committed Mar 16, 2015
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    9adf3f0 View commit details
Showing with 35 additions and 23 deletions.
  1. +2 −2 mibuild/generic_platform.py
  2. +33 −21 migen/fhdl/verilog.py
4 changes: 2 additions & 2 deletions mibuild/generic_platform.py
Original file line number Diff line number Diff line change
@@ -274,11 +274,11 @@ def _get_source(self, fragment, gen_fn):

def get_verilog(self, fragment, **kwargs):
return self._get_source(fragment, lambda f: verilog.convert(f, self.constraint_manager.get_io_signals(),
return_ns=True, create_clock_domains=False, **kwargs))
return_ns=True, create_clock_domains=False, simulation=False, **kwargs))

def get_edif(self, fragment, cell_library, vendor, device, **kwargs):
return self._get_source(fragment, lambda f: edif.convert(f, self.constraint_manager.get_io_signals(),
cell_library, vendor, device, return_ns=True, **kwargs))
cell_library, vendor, device, return_ns=True, simulation=False, **kwargs))

def build(self, fragment):
raise NotImplementedError("GenericPlatform.build must be overloaded")
54 changes: 33 additions & 21 deletions migen/fhdl/verilog.py
Original file line number Diff line number Diff line change
@@ -175,39 +175,42 @@ def _printheader(f, ios, name, ns):
r += "\n"
return r

def _printcomb(f, ns, display_run):
def _printcomb(f, ns, simulation, display_run):
r = ""
if f.comb:
# Generate a dummy event to get the simulator
# to run the combinatorial process once at the beginning.
syn_off = "// synthesis translate_off\n"
syn_on = "// synthesis translate_on\n"
dummy_s = Signal(name_override="dummy_s")
r += syn_off
r += "reg " + _printsig(ns, dummy_s) + ";\n"
r += "initial " + ns.get_name(dummy_s) + " <= 1'd0;\n"
r += syn_on
if simulation:
# Generate a dummy event to get the simulator
# to run the combinatorial process once at the beginning.
syn_off = "// synthesis translate_off\n"
syn_on = "// synthesis translate_on\n"
dummy_s = Signal(name_override="dummy_s")
r += syn_off
r += "reg " + _printsig(ns, dummy_s) + ";\n"
r += "initial " + ns.get_name(dummy_s) + " <= 1'd0;\n"
r += syn_on

groups = group_by_targets(f.comb)

for n, g in enumerate(groups):
if len(g[1]) == 1 and isinstance(g[1][0], _Assign):
r += "assign " + _printnode(ns, _AT_BLOCKING, 0, g[1][0])
else:
dummy_d = Signal(name_override="dummy_d")
r += "\n" + syn_off
r += "reg " + _printsig(ns, dummy_d) + ";\n"
r += syn_on
if simulation:
dummy_d = Signal(name_override="dummy_d")
r += "\n" + syn_off
r += "reg " + _printsig(ns, dummy_d) + ";\n"
r += syn_on

r += "always @(*) begin\n"
if display_run:
r += "\t$display(\"Running comb block #" + str(n) + "\");\n"
for t in g[0]:
r += "\t" + ns.get_name(t) + " <= " + _printexpr(ns, t.reset)[0] + ";\n"
r += _printnode(ns, _AT_NONBLOCKING, 1, g[1])
r += syn_off
r += "\t" + ns.get_name(dummy_d) + " <= " + ns.get_name(dummy_s) + ";\n"
r += syn_on
if simulation:
r += syn_off
r += "\t" + ns.get_name(dummy_d) + " <= " + ns.get_name(dummy_s) + ";\n"
r += syn_on
r += "end\n"
r += "\n"
return r
@@ -276,17 +279,26 @@ def _printinit(f, ios, ns):
- ios \
- list_targets(f) \
- list_special_ios(f, False, True, True)
wires = (_list_comb_wires(f) | list_special_ios(f, True, False, False)) \
- ios \
- list_targets(f) \
- list_special_ios(f, False, True, True)
if signals:
r += "initial begin\n"
for s in sorted(signals, key=lambda x: x.huid):
r += "\t" + ns.get_name(s) + " <= " + _printexpr(ns, s.reset)[0] + ";\n"
r += "end\n\n"
if s in wires:
r += "assign" + ns.get_name(s) + " = " + _printexpr(ns, s.reset)[0] + ";\n"
r += "always @(*) begin\n"
for s in sorted(signals, key=lambda x: x.huid):
if s not in wires:
r += "\t" + ns.get_name(s) + " <= " + _printexpr(ns, s.reset)[0] + ";\n"
r += "end\n"
return r

def convert(f, ios=None, name="top",
return_ns=False,
special_overrides=dict(),
create_clock_domains=True,
simulation=True,
display_run=False):
if not isinstance(f, _Fragment):
f = f.get_fragment()
@@ -316,7 +328,7 @@ def convert(f, ios=None, name="top",

r = "/* Machine-generated using Migen */\n"
r += _printheader(f, ios, name, ns)
r += _printcomb(f, ns, display_run)
r += _printcomb(f, ns, simulation, display_run)
r += _printsync(f, ns)
r += _printspecials(special_overrides, f.specials - lowered_specials, ns)
r += _printinit(f, ios, ns)