targets/simple: manual instantiation of CRG (automatic insertion work…

…s for BaseSoC but not for MiniSoC since this one define clock_domains)
m-labs · Mar 17, 2015 · b2f32ad · b2f32ad
1 parent faf185d
commit b2f32ad
Showing 1 changed file with 2 additions and 0 deletions.
diff --git a/targets/simple.py b/targets/simple.py
@@ -1,5 +1,6 @@
 from migen.fhdl.std import *
 from migen.bus import wishbone
+from migen.genlib.io import CRG
 
 from misoclib.soc import SoC, mem_decoder
 from misoclib.com.liteeth.phy import LiteEthPHY
@@ -12,6 +13,7 @@ def __init__(self, platform, **kwargs):
 			with_rom=True,
 			with_main_ram=True, main_ram_size=16*1024,
 			**kwargs)
+		self.submodules.crg = CRG(platform.request(platform.default_clk_name))
 
 class MiniSoC(BaseSoC):
 	csr_map = {