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base repository: m-labs/migen
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  • 4 commits
  • 4 files changed
  • 1 contributor

Commits on Mar 18, 2015

  1. fhdl/verilog: revert "fhdl/verilog: add simulation parameter to avoid…

    … simulation tricks in synthetizable code"
    
    This probably breaks simulation with Icarus Verilog (and others simulators?)
    enjoy-digital committed Mar 18, 2015
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    ea9c1b8 View commit details
  2. fhdl/verilog: change the way we initialize reg: reg name = init_value;

    This allows simplifications (init in _printsync and _printinit no longer needed)
    enjoy-digital committed Mar 18, 2015
    2
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    c0fb0ef View commit details
  3. 4
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    5a9afee View commit details
  4. mibuild/lattice/diamond: add verilog include path (thanks Lattice's F…

    …AE since it's not documented)
    enjoy-digital committed Mar 18, 2015
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    3aee58f View commit details
Showing with 33 additions and 45 deletions.
  1. +2 −2 mibuild/generic_platform.py
  2. +2 −0 mibuild/lattice/diamond.py
  3. +11 −2 migen/fhdl/specials.py
  4. +18 −41 migen/fhdl/verilog.py
4 changes: 2 additions & 2 deletions mibuild/generic_platform.py
Original file line number Diff line number Diff line change
@@ -274,11 +274,11 @@ def _get_source(self, fragment, gen_fn):

def get_verilog(self, fragment, **kwargs):
return self._get_source(fragment, lambda f: verilog.convert(f, self.constraint_manager.get_io_signals(),
return_ns=True, create_clock_domains=False, simulation=False, **kwargs))
return_ns=True, create_clock_domains=False, **kwargs))

def get_edif(self, fragment, cell_library, vendor, device, **kwargs):
return self._get_source(fragment, lambda f: edif.convert(f, self.constraint_manager.get_io_signals(),
cell_library, vendor, device, return_ns=True, simulation=False, **kwargs))
cell_library, vendor, device, return_ns=True, **kwargs))

def build(self, fragment):
raise NotImplementedError("GenericPlatform.build must be overloaded")
2 changes: 2 additions & 0 deletions mibuild/lattice/diamond.py
Original file line number Diff line number Diff line change
@@ -40,6 +40,8 @@ def _build_lpf(named_sc, named_pc):
def _build_files(device, sources, vincpaths, build_name):
tcl = []
tcl.append("prj_project new -name \"%s\" -impl \"implementation\" -dev %s -synthesis \"synplify\"" %(build_name, device))
for path in vincpaths:
tcl.append("prj_impl option {include path} {\"" + path.replace("\\", "/") + "\"}")
for filename, language in sources:
tcl.append("prj_src add \"" + filename.replace("\\", "/") + "\"")
tcl.append("prj_run Synthesis -impl implementation -forceOne")
13 changes: 11 additions & 2 deletions migen/fhdl/specials.py
Original file line number Diff line number Diff line change
@@ -307,11 +307,20 @@ def gn(e):
r += "\n"

if memory.init is not None:
memory_filename = gn(memory) + ".init"

# XXX move I/O to mibuild?
# (Implies mem init won't work with simple Migen examples?)
f = open(memory_filename, "w")
for d in memory.init:
f.write("{:x}\n".format(d))
f.close()

r += "initial begin\n"
for i, c in enumerate(memory.init):
r += "\t" + gn(memory) + "[" + str(i) + "] <= " + str(memory.width) + "'d" + str(c) + ";\n"
r += "$readmemh(\"" + memory_filename + "\", " + gn(memory) + ");\n"
r += "end\n\n"


return r

class SynthesisDirective(Special):
59 changes: 18 additions & 41 deletions migen/fhdl/verilog.py
Original file line number Diff line number Diff line change
@@ -171,57 +171,49 @@ def _printheader(f, ios, name, ns):
if sig in wires:
r += "wire " + _printsig(ns, sig) + ";\n"
else:
r += "reg " + _printsig(ns, sig) + ";\n"
r += "reg " + _printsig(ns, sig) + " = " + _printexpr(ns, sig.reset)[0] + ";\n"
r += "\n"
return r

def _printcomb(f, ns, simulation, display_run):
def _printcomb(f, ns, display_run):
r = ""
if f.comb:
if simulation:
# Generate a dummy event to get the simulator
# to run the combinatorial process once at the beginning.
syn_off = "// synthesis translate_off\n"
syn_on = "// synthesis translate_on\n"
dummy_s = Signal(name_override="dummy_s")
r += syn_off
r += "reg " + _printsig(ns, dummy_s) + ";\n"
r += "initial " + ns.get_name(dummy_s) + " <= 1'd0;\n"
r += syn_on
# Generate a dummy event to get the simulator
# to run the combinatorial process once at the beginning.
syn_off = "// synthesis translate_off\n"
syn_on = "// synthesis translate_on\n"
dummy_s = Signal(name_override="dummy_s")
r += syn_off
r += "reg " + _printsig(ns, dummy_s) + " = 1'd0;\n"
r += syn_on

groups = group_by_targets(f.comb)

for n, g in enumerate(groups):
if len(g[1]) == 1 and isinstance(g[1][0], _Assign):
r += "assign " + _printnode(ns, _AT_BLOCKING, 0, g[1][0])
else:
if simulation:
dummy_d = Signal(name_override="dummy_d")
r += "\n" + syn_off
r += "reg " + _printsig(ns, dummy_d) + ";\n"
r += syn_on
dummy_d = Signal(name_override="dummy_d")
r += "\n" + syn_off
r += "reg " + _printsig(ns, dummy_d) + ";\n"
r += syn_on

r += "always @(*) begin\n"
if display_run:
r += "\t$display(\"Running comb block #" + str(n) + "\");\n"
for t in g[0]:
r += "\t" + ns.get_name(t) + " <= " + _printexpr(ns, t.reset)[0] + ";\n"
r += _printnode(ns, _AT_NONBLOCKING, 1, g[1])
if simulation:
r += syn_off
r += "\t" + ns.get_name(dummy_d) + " <= " + ns.get_name(dummy_s) + ";\n"
r += syn_on
r += syn_off
r += "\t" + ns.get_name(dummy_d) + " <= " + ns.get_name(dummy_s) + ";\n"
r += syn_on
r += "end\n"
r += "\n"
return r

def _printsync(f, ns):
r = ""
for k, v in sorted(f.sync.items(), key=itemgetter(0)):
if f.clock_domains[k].rst is None:
r += "initial begin\n"
r += _printnode(ns, _AT_SIGNAL, 1, generate_reset(ResetSignal(k), v))
r += "end\n\n"
r += "always @(posedge " + ns.get_name(f.clock_domains[k].clk) + ") begin\n"
r += _printnode(ns, _AT_SIGNAL, 1, v)
r += "end\n\n"
@@ -273,24 +265,10 @@ def _printspecials(overrides, specials, ns):
r += pr
return r

def _printinit(f, ios, ns):
r = ""
signals = (list_signals(f) | list_special_ios(f, True, False, False)) \
- ios \
- list_targets(f) \
- list_special_ios(f, False, True, True)
if signals:
r += "initial begin\n"
for s in sorted(signals, key=lambda x: x.huid):
r += "\t" + ns.get_name(s) + " <= " + _printexpr(ns, s.reset)[0] + ";\n"
r += "end\n\n"
return r

def convert(f, ios=None, name="top",
return_ns=False,
special_overrides=dict(),
create_clock_domains=True,
simulation=True,
display_run=False):
if not isinstance(f, _Fragment):
f = f.get_fragment()
@@ -320,10 +298,9 @@ def convert(f, ios=None, name="top",

r = "/* Machine-generated using Migen */\n"
r += _printheader(f, ios, name, ns)
r += _printcomb(f, ns, simulation, display_run)
r += _printcomb(f, ns, display_run)
r += _printsync(f, ns)
r += _printspecials(special_overrides, f.specials - lowered_specials, ns)
r += _printinit(f, ios, ns)
r += "endmodule\n"

if return_ns: