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- 4 commits
- 4 files changed
- 1 contributor
Commits on Mar 18, 2015
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fhdl/verilog: revert "fhdl/verilog: add simulation parameter to avoid…
… simulation tricks in synthetizable code" This probably breaks simulation with Icarus Verilog (and others simulators?)
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fhdl/verilog: change the way we initialize reg: reg name = init_value;
This allows simplifications (init in _printsync and _printinit no longer needed)
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mibuild/lattice/diamond: add verilog include path (thanks Lattice's F…
…AE since it's not documented)
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