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enjoy-digitalenjoy-digital
committedMar 16, 2015
mibuild: add initial Lattice Diamond support (with ECP3 Versa board platform skeleton)
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0.9.20.1
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‎mibuild/lattice/__init__.py

Whitespace-only changes.

‎mibuild/lattice/diamond.py

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# This file is Copyright (c) 2015 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import os, subprocess, shutil
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from migen.fhdl.structure import _Fragment
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from mibuild.generic_platform import *
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from mibuild import tools
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def _format_constraint(c):
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if isinstance(c, Pins):
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return ("LOCATE COMP ", " SITE " + "\"" + c.identifiers[0] + "\"")
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elif isinstance(c, IOStandard):
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return ("IOBUF PORT ", " IO_TYPE=" + c.name)
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elif isinstance(c, Misc):
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return c.misc
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def _format_lpf(signame, pin, others, resname):
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fmt_c = [_format_constraint(c) for c in ([Pins(pin)] + others)]
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r = ""
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for pre, suf in fmt_c:
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r += pre + "\""+ signame +"\"" + suf + ";\n"
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return r
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def _build_lpf(named_sc, named_pc):
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r = "BLOCK RESETPATHS;\n"
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r += "BLOCK ASYNCPATHS;\n"
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for sig, pins, others, resname in named_sc:
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if len(pins) > 1:
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for i, p in enumerate(pins):
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r += _format_lpf(sig + "[" + str(i) + "]", p, others, resname)
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else:
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r += _format_lpf(sig, pins[0], others, resname)
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if named_pc:
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r += "\n" + "\n\n".join(named_pc)
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return r
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def _build_files(device, sources, vincpaths, build_name):
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tcl = []
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tcl.append("prj_project new -name \"%s\" -impl \"implementation\" -dev %s -synthesis \"synplify\"" %(build_name, device))
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for filename, language in sources:
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tcl.append("prj_src add \"" + filename.replace("\\", "/") + "\"")
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tcl.append("prj_run Synthesis -impl implementation -forceOne")
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tcl.append("prj_run Translate -impl implementation")
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tcl.append("prj_run Map -impl implementation")
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tcl.append("prj_run PAR -impl implementation")
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tcl.append("prj_run Export -impl implementation -task Bitgen")
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tools.write_to_file(build_name + ".tcl", "\n".join(tcl))
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def _run_diamond(build_name, source, ver=None):
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if sys.platform == "win32" or sys.platform == "cygwin":
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build_script_contents = "REM Autogenerated by mibuild\n"
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build_script_contents = "pnmainc " + build_name + ".tcl\n"
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build_script_file = "build_" + build_name + ".bat"
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tools.write_to_file(build_script_file, build_script_contents)
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r = subprocess.call([build_script_file])
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shutil.copy(os.path.join("implementation", build_name + "_implementation.bit"), build_name + ".bit")
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else:
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raise NotImplementedError()
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if r != 0:
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raise OSError("Subprocess failed")
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class LatticeDiamondPlatform(GenericPlatform):
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bitstream_ext = ".bit"
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def build(self, fragment, build_dir="build", build_name="top",
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diamond_path="/opt/Diamond", run=True):
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tools.mkdir_noerror(build_dir)
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os.chdir(build_dir)
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if not isinstance(fragment, _Fragment):
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fragment = fragment.get_fragment()
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self.finalize(fragment)
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v_src, vns = self.get_verilog(fragment)
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named_sc, named_pc = self.resolve_signals(vns)
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v_file = build_name + ".v"
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tools.write_to_file(v_file, v_src)
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sources = self.sources + [(v_file, "verilog")]
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_build_files(self.device, sources, self.verilog_include_paths, build_name)
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tools.write_to_file(build_name + ".lpf", _build_lpf(named_sc, named_pc))
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if run:
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_run_diamond(build_name, diamond_path)
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os.chdir("..")
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return vns
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def add_period_constraint(self, clk, period):
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# TODO: handle differential clk
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self.add_platform_command("""FREQUENCY PORT "{clk}" {freq} MHz;""".format(freq=str(float(1/period)*1000), clk="{clk}"), clk=clk)

‎mibuild/lattice/programmer.py

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import os, subprocess
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from mibuild.generic_programmer import GenericProgrammer
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from mibuild import tools
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# XXX Lattice programmer need an .xcf file, will need clean up and support for more parameters
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_xcf_template = """
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<?xml version='1.0' encoding='utf-8' ?>
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<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
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<ispXCF version="3.4.1">
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<Comment></Comment>
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<Chain>
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<Comm>JTAG</Comm>
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<Device>
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<SelectedProg value="TRUE"/>
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<Pos>1</Pos>
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<Vendor>Lattice</Vendor>
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<Family>LatticeECP3</Family>
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<Name>LFE3-35EA</Name>
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<File>{bitstream_file}</File>
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<Operation>Fast Program</Operation>
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</Device>
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</Chain>
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<ProjectOptions>
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<Program>SEQUENTIAL</Program>
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<Process>ENTIRED CHAIN</Process>
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<OperationOverride>No Override</OperationOverride>
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<StartTAP>TLR</StartTAP>
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<EndTAP>TLR</EndTAP>
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<VerifyUsercode value="FALSE"/>
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</ProjectOptions>
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<CableOptions>
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<CableName>USB2</CableName>
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<PortAdd>FTUSB-0</PortAdd>
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<USBID>Dual RS232-HS A Location 0000 Serial A</USBID>
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<JTAGPinSetting>
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TRST ABSENT;
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ISPEN ABSENT;
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</JTAGPinSetting>
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</CableOptions>
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</ispXCF>
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"""
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class LatticeProgrammer(GenericProgrammer):
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needs_bitreverse = False
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def load_bitstream(self, bitstream_file):
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xcf_file = bitstream_file.replace(".bit", ".xcf")
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xcf_content = _xcf_template.format(bitstream_file=bitstream_file)
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tools.write_to_file(xcf_file, xcf_content)
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subprocess.call(["pgrcmd", "-infile", xcf_file])

‎mibuild/platforms/versa.py

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# This file is Copyright (c) 2013 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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from mibuild.generic_platform import *
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from mibuild.lattice.diamond import LatticeDiamondPlatform
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from mibuild.lattice.programmer import LatticeProgrammer
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_io = [
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("clk100", 0, Pins("L5"), IOStandard("LVDS25")),
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("user_led", 0, Pins("Y20"), IOStandard("LVCMOS33")),
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("user_led", 1, Pins("AA21"), IOStandard("LVCMOS33")),
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("user_led", 2, Pins("U18"), IOStandard("LVCMOS33")),
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("user_led", 3, Pins("U19"), IOStandard("LVCMOS33")),
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("user_led", 4, Pins("W19"), IOStandard("LVCMOS33")),
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("user_led", 5, Pins("V19"), IOStandard("LVCMOS33")),
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("user_led", 6, Pins("AB20"), IOStandard("LVCMOS33")),
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("user_led", 7, Pins("AA20"), IOStandard("LVCMOS33")),
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("serial", 0,
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Subsignal("tx", Pins("B11"), IOStandard("LVCMOS33")), # X4 IO0
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Subsignal("rx", Pins("B12"), IOStandard("LVCMOS33")), # X4 IO1
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),
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]
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class Platform(LatticeDiamondPlatform):
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default_clk_name = "clk100"
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default_clk_period = 10
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def __init__(self):
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LatticeDiamondPlatform.__init__(self, "LFE3-35EA-6FN484C", _io)
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def create_programmer(self):
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return LatticeProgrammer()

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