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base repository: m-labs/migen
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head repository: m-labs/migen
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compare: e07b7f632cef
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  • 3 commits
  • 2 files changed
  • 1 contributor

Commits on Mar 17, 2015

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    022ac26 View commit details
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Showing with 28 additions and 4 deletions.
  1. +21 −2 mibuild/lattice/common.py
  2. +7 −2 migen/fhdl/specials.py
23 changes: 21 additions & 2 deletions mibuild/lattice/common.py
Original file line number Diff line number Diff line change
@@ -1,10 +1,28 @@
from migen.fhdl.std import *
from migen.genlib.io import *

from migen.genlib.resetsync import AsyncResetSynchronizer

class LatticeAsyncResetSynchronizerImpl(Module):
def __init__(self, cd, async_reset):
rst1 = Signal()
self.specials += [
Instance("FD1S3BX", i_D=0, i_PD=async_reset,
i_CK=cd.clk, o_Q=rst1),
Instance("FD1S3BX", i_D=rst1, i_PD=async_reset,
i_CK=cd.clk, o_Q=cd.rst)
]

class LatticeAsyncResetSynchronizer:
@staticmethod
def lower(dr):
return LatticeAsyncResetSynchronizerImpl(dr.cd, dr.async_reset)

class LatticeDDROutputImpl(Module):
def __init__(self, i1, i2, o, clk):
self.specials += Instance("ODDRA",
i_CLK=clk, i_RST=0,
self.specials += Instance("ODDRXD1",
synthesis_directive="ODDRAPPS=\"SCLK_ALIGNED\"",
i_SCLK=clk,
i_DA=i1, i_DB=i2, o_Q=o,
)

@@ -14,5 +32,6 @@ def lower(dr):
return LatticeDDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk)

lattice_special_overrides = {
AsyncResetSynchronizer: LatticeAsyncResetSynchronizer,
DDROutput: LatticeDDROutput
}
9 changes: 7 additions & 2 deletions migen/fhdl/specials.py
Original file line number Diff line number Diff line change
@@ -89,14 +89,15 @@ def __init__(self, name, value):
class PreformattedParam(str):
pass

def __init__(self, of, *items, name="", **kwargs):
def __init__(self, of, *items, name="", synthesis_directive=None, **kwargs):
Special.__init__(self)
self.of = of
if name:
self.name_override = name
else:
self.name_override = of
self.items = list(items)
self.synthesis_directive = synthesis_directive
for k, v in sorted(kwargs.items(), key=itemgetter(0)):
item_type, item_name = k.split("_", maxsplit=1)
item_class = {
@@ -159,7 +160,11 @@ def emit_verilog(instance, ns):
r += "\t." + name_inst + "(" + name_design + ")"
if not firstp:
r += "\n"
r += ");\n\n"
if instance.synthesis_directive is not None:
synthesis_directive = "/* synthesis {} */".format(instance.synthesis_directive)
r += ")" + synthesis_directive + ";\n\n"
else:
r += ");\n\n"
return r

(READ_FIRST, WRITE_FIRST, NO_CHANGE) = range(3)