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base repository: m-labs/misoc
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compare: 2327710387e7
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  • 3 commits
  • 3 files changed
  • 1 contributor

Commits on Mar 17, 2015

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Showing with 5 additions and 18 deletions.
  1. +1 −1 misoclib/com/liteeth/example_designs/make.py
  2. +2 −16 misoclib/com/liteeth/example_designs/targets/base.py
  3. +2 −1 misoclib/com/liteeth/phy/gmii.py
2 changes: 1 addition & 1 deletion misoclib/com/liteeth/example_designs/make.py
Original file line number Diff line number Diff line change
@@ -38,7 +38,7 @@ def _get_args():
parser.add_argument("-s", "--sub-target", default="", help="variant of the Core type to build")
parser.add_argument("-p", "--platform", default=None, help="platform to build for")
parser.add_argument("-Ot", "--target-option", default=[], nargs=2, action="append", help="set target-specific option")
parser.add_argument("-Op", "--platform-option", default=[("programmer", "vivado")], nargs=2, action="append", help="set platform-specific option")
parser.add_argument("-Op", "--platform-option", default=[], nargs=2, action="append", help="set platform-specific option")
parser.add_argument("--csr_csv", default="./test/csr.csv", help="CSV file to save the CSR map into")

parser.add_argument("action", nargs="+", help="specify an action")
18 changes: 2 additions & 16 deletions misoclib/com/liteeth/example_designs/targets/base.py
Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
from migen.bus import wishbone
from migen.bank.description import *
from migen.genlib.io import CRG

from misoclib.soc import SoC
from misoclib.tools.litescope.common import *
@@ -12,20 +13,6 @@
from misoclib.com.liteeth.phy.gmii import LiteEthPHYGMII
from misoclib.com.liteeth.core import LiteEthUDPIPCore

class _CRG(Module):
def __init__(self, clk_in):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)

# Power on Reset (vendor agnostic)
rst_n = Signal()
self.sync.por += rst_n.eq(1)
self.comb += [
self.cd_sys.clk.eq(clk_in),
self.cd_por.clk.eq(clk_in),
self.cd_sys.rst.eq(~rst_n)
]

class BaseSoC(SoC, AutoCSR):
csr_map = {
"phy": 11,
@@ -44,8 +31,7 @@ def __init__(self, platform, clk_freq=166*1000000,
with_identifier=True,
with_timer=False
)
clk_in = platform.request(platform.default_clk_name)
self.submodules.crg = _CRG(clk_in if not hasattr(clk_in, "p") else clk_in.p)
self.submodules.crg = CRG(platform.request(platform.default_clk_name))

# wishbone SRAM (to test Wishbone over UART and Etherbone)
self.submodules.sram = wishbone.SRAM(1024)
3 changes: 2 additions & 1 deletion misoclib/com/liteeth/phy/gmii.py
Original file line number Diff line number Diff line change
@@ -7,8 +7,9 @@ class LiteEthPHYGMIITX(Module):
def __init__(self, pads):
self.sink = sink = Sink(eth_phy_description(8))
###
if hasattr(pads, "tx_er"):
self.sync += pads.tx_er.eq(0)
self.sync += [
pads.tx_er.eq(0),
pads.tx_en.eq(sink.stb),
pads.tx_data.eq(sink.data)
]