|
4 | 4 | from migen.fhdl.std import *
|
5 | 5 | from migen.fhdl.specials import SynthesisDirective
|
6 | 6 | from migen.genlib.cdc import *
|
| 7 | +from migen.genlib.resetsync import AsyncResetSynchronizer |
7 | 8 | from mibuild.generic_platform import GenericPlatform
|
8 | 9 | from mibuild import tools
|
9 | 10 |
|
@@ -66,13 +67,29 @@ class XilinxMultiReg:
|
66 | 67 | def lower(dr):
|
67 | 68 | return XilinxMultiRegImpl(dr.i, dr.o, dr.odomain, dr.n)
|
68 | 69 |
|
| 70 | +class XilinxAsyncResetSynchronizerImpl(Module): |
| 71 | + def __init__(self, cd, async_reset): |
| 72 | + rst1 = Signal() |
| 73 | + self.specials += [ |
| 74 | + Instance("FDPE", p_INIT=1, i_D=0, i_PRE=async_reset, |
| 75 | + i_C=cd.clk, o_Q=rst1), |
| 76 | + Instance("FDPE", p_INIT=1, i_D=rst1, i_PRE=async_reset, |
| 77 | + i_C=cd.clk, o_Q=cd.rst) |
| 78 | + ] |
| 79 | + |
| 80 | +class XilinxAsyncResetSynchronizer: |
| 81 | + staticmethod |
| 82 | + def lower(dr): |
| 83 | + return XilinxAsyncResetSynchronizerImpl(dr.cd, dr.async_reset) |
| 84 | + |
69 | 85 | class XilinxGenericPlatform(GenericPlatform):
|
70 | 86 | bitstream_ext = ".bit"
|
71 | 87 |
|
72 | 88 | def get_verilog(self, *args, special_overrides=dict(), **kwargs):
|
73 | 89 | so = {
|
74 |
| - NoRetiming: XilinxNoRetiming, |
75 |
| - MultiReg: XilinxMultiReg |
| 90 | + NoRetiming: XilinxNoRetiming, |
| 91 | + MultiReg: XilinxMultiReg, |
| 92 | + AsyncResetSynchronizer: XilinxAsyncResetSynchronizer |
76 | 93 | }
|
77 | 94 | so.update(special_overrides)
|
78 | 95 | return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs)
|
|
0 commit comments