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base repository: m-labs/misoc
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compare: c95b9d6d7683
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Dec 12, 2013

  1. make.py: update description

    Sebastien Bourdeauducq committed Dec 12, 2013

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    jluttine Jaakko Luttinen
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  2. gensoc: use add_verilog_include_path

    Sebastien Bourdeauducq committed Dec 12, 2013

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    jluttine Jaakko Luttinen
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Showing with 2 additions and 2 deletions.
  1. +1 −1 make.py
  2. +1 −1 misoclib/gensoc/__init__.py
2 changes: 1 addition & 1 deletion make.py
View file
Original file line number Diff line number Diff line change
@@ -11,7 +11,7 @@
import jtag

def _get_args():
parser = argparse.ArgumentParser(description="MiSoC - a high performance SoC based on Migen.")
parser = argparse.ArgumentParser(description="MiSoC - a high performance and small footprint SoC based on Migen.")

parser.add_argument("-p", "--platform", default="mixxeo", help="platform to build for")
parser.add_argument("-t", "--target", default="mlabs_video", help="SoC type to build")
2 changes: 1 addition & 1 deletion misoclib/gensoc/__init__.py
View file
Original file line number Diff line number Diff line change
@@ -66,7 +66,7 @@ def __init__(self, platform, clk_freq, cpu_reset_address, sram_size, l2_size=0):
"lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",
"lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
"lm32_dcache.v", "lm32_debug.v", "lm32_itlb.v", "lm32_dtlb.v")
platform.add_sources(os.path.join("verilog", "lm32"), "lm32_config.v")
platform.add_verilog_include_path(os.path.join("verilog", "lm32"))

def register_rom(self, rom_wb_if, bios_size=0x8000):
if self._rom_registered: