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base repository: m-labs/misoc
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head repository: m-labs/misoc
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compare: 20207c9c3203
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  • 3 commits
  • 10 files changed
  • 1 contributor

Commits on Mar 22, 2015

  1. liteusb: fix imports

    enjoy-digital committed Mar 22, 2015
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    ed5746a View commit details
  2. Copy the full SHA
    c77562f View commit details
  3. liteusb: give more generic names to modules: FtdiXXX becomes LiteUSBX…

    …XX, move PHY outside of core (builds on minispartan6)
    enjoy-digital committed Mar 22, 2015
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    20207c9 View commit details
4 changes: 2 additions & 2 deletions misoclib/com/liteusb/common.py
Original file line number Diff line number Diff line change
@@ -16,12 +16,12 @@
("d", 8)
]

class FtdiPipe:
class LiteUSBPipe:
def __init__(self, layout):
self.sink = Sink(layout)
self.source = Source(layout)

class FtdiTimeout(Module):
class LiteUSBTimeout(Module):
def __init__(self, clk_freq, length):
cnt_max = int(clk_freq*length)
width = bits_for(cnt_max)
8 changes: 4 additions & 4 deletions misoclib/com/liteusb/core/__init__.py
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
from liteusb.ftdi.uart import FtdiUART
from liteusb.ftdi.dma import FtdiDMA
from liteusb.ftdi.com import FtdiCom
from liteusb.ftdi.crc import FtdiCRC32
from misoclib.com.liteusb.frontend.uart import LiteUSBUART
from misoclib.com.liteusb.frontend.dma import LiteUSBDMA
from misoclib.com.liteusb.core.com import LiteUSBCom
from misoclib.com.liteusb.core.crc import LiteUSBCRC32
24 changes: 11 additions & 13 deletions misoclib/com/liteusb/core/com.py
Original file line number Diff line number Diff line change
@@ -1,28 +1,26 @@
from migen.fhdl.std import *
from migen.flow.actor import *

from liteusb.ftdi.std import *
from liteusb.ftdi.crossbar import FtdiCrossbar
from liteusb.ftdi.packetizer import FtdiPacketizer
from liteusb.ftdi.depacketizer import FtdiDepacketizer
from liteusb.ftdi.phy import FtdiPHY
from misoclib.com.liteusb.common import *
from misoclib.com.liteusb.frontend.crossbar import LiteUSBCrossbar
from misoclib.com.liteusb.core.packetizer import LiteUSBPacketizer
from misoclib.com.liteusb.core.depacketizer import LiteUSBDepacketizer

class FtdiCom(Module):
def __init__(self, pads, *ports):
class LiteUSBCom(Module):
def __init__(self, phy, *ports):
# crossbar
self.submodules.crossbar = FtdiCrossbar(list(ports))
self.submodules.crossbar = LiteUSBCrossbar(list(ports))

# packetizer / depacketizer
self.submodules.packetizer = FtdiPacketizer()
self.submodules.depacketizer = FtdiDepacketizer()
self.submodules.packetizer = LiteUSBPacketizer()
self.submodules.depacketizer = LiteUSBDepacketizer()
self.comb += [
self.crossbar.slave.source.connect(self.packetizer.sink),
self.depacketizer.source.connect(self.crossbar.slave.sink)
]

# phy
self.submodules.phy = FtdiPHY(pads)
self.comb += [
self.packetizer.source.connect(self.phy.sink),
self.phy.source.connect(self.depacketizer.sink)
self.packetizer.source.connect(phy.sink),
phy.source.connect(self.depacketizer.sink)
]
5 changes: 2 additions & 3 deletions misoclib/com/liteusb/core/crc.py
Original file line number Diff line number Diff line change
@@ -1,4 +1,3 @@

from collections import OrderedDict
from migen.fhdl.std import *
from migen.genlib.fsm import FSM, NextState
@@ -7,7 +6,7 @@
from migen.flow.actor import Sink, Source
from migen.actorlib.fifo import SyncFIFO

from liteusb.ftdi.std import *
from misoclib.com.liteusb.common import *

class CRCEngine(Module):
"""Cyclic Redundancy Check Engine
@@ -284,7 +283,7 @@ class CRC32Checker(CRCChecker):
def __init__(self, layout):
CRCChecker.__init__(self, CRC32, layout)

class FtdiCRC32(Module):
class LiteUSBCRC32(Module):
def __init__(self, tag):
self.tag = tag

8 changes: 4 additions & 4 deletions misoclib/com/liteusb/core/depacketizer.py
Original file line number Diff line number Diff line change
@@ -2,9 +2,9 @@
from migen.actorlib.structuring import *
from migen.genlib.fsm import FSM, NextState

from liteusb.ftdi.std import *
from misoclib.com.liteusb.common import *

class FtdiDepacketizer(Module):
class LiteUSBDepacketizer(Module):
def __init__(self, timeout=10):
self.sink = sink = Sink(phy_layout)
self.source = source = Source(user_layout)
@@ -53,7 +53,7 @@ def __init__(self, timeout=10):
header_pack.source.ack.eq(1),
)

self.submodules.timeout = FtdiTimeout(60000000, timeout)
self.submodules.timeout = LiteUSBTimeout(60000000, timeout)
self.comb += self.timeout.clear.eq(fsm.ongoing("WAIT_SOP"))

fsm.act("RECEIVE_HEADER",
@@ -137,7 +137,7 @@ def do_simulation(self, selfp):
class TB(Module):
def __init__(self):
self.submodules.source = DepacketizerSourceModel(src_data)
self.submodules.dut = FtdiDepacketizer()
self.submodules.dut = LiteUSBDepacketizer()
self.submodules.sink = DepacketizerSinkModel()

self.comb += [
6 changes: 3 additions & 3 deletions misoclib/com/liteusb/core/packetizer.py
Original file line number Diff line number Diff line change
@@ -2,9 +2,9 @@
from migen.actorlib.structuring import *
from migen.genlib.fsm import FSM, NextState

from liteusb.ftdi.std import *
from misoclib.com.liteusb.common import *

class FtdiPacketizer(Module):
class LiteUSBPacketizer(Module):
def __init__(self):
self.sink = sink = Sink(user_layout)
self.source = source = Source(phy_layout)
@@ -132,7 +132,7 @@ def do_simulation(self, selfp):
class TB(Module):
def __init__(self):
self.submodules.source = PacketizerSourceModel(src_data)
self.submodules.dut = FtdiPacketizer()
self.submodules.dut = LiteUSBPacketizer()
self.submodules.sink = PacketizerSinkModel()

self.comb +=[
6 changes: 3 additions & 3 deletions misoclib/com/liteusb/frontend/crossbar.py
Original file line number Diff line number Diff line change
@@ -2,12 +2,12 @@
from migen.genlib.roundrobin import *
from migen.genlib.record import Record

from liteusb.ftdi.std import *
from misoclib.com.liteusb.common import *

class FtdiCrossbar(Module):
class LiteUSBCrossbar(Module):
def __init__(self, masters, slave=None):
if slave is None:
slave = FtdiPipe(user_layout)
slave = LiteUSBPipe(user_layout)
self.slave = slave

# masters --> slave arbitration
12 changes: 6 additions & 6 deletions misoclib/com/liteusb/frontend/dma.py
Original file line number Diff line number Diff line change
@@ -8,9 +8,9 @@

from misoclib.mem.sdram.frontend import dma_lasmi

from liteusb.ftdi.std import *
from misoclib.com.liteusb.common import *

class FtdiDMAWriter(Module, AutoCSR):
class LiteUSBDMAWriter(Module, AutoCSR):
def __init__(self, lasmim):
self.sink = sink = Sink(user_layout)

@@ -50,7 +50,7 @@ def __init__(self, lasmim):
self._crc_failed.status.eq(sink.error)
)

class FtdiDMAReader(Module, AutoCSR):
class LiteUSBDMAReader(Module, AutoCSR):
def __init__(self, lasmim, tag):
self.source = source = Source(user_layout)

@@ -89,12 +89,12 @@ def __init__(self, lasmim, tag):
self.ev.finalize()
self.comb += self.ev.done.trigger.eq(source.stb & source.eop)

class FtdiDMA(Module, AutoCSR):
class LiteUSBDMA(Module, AutoCSR):
def __init__(self, lasmim_ftdi_dma_wr, lasmim_ftdi_dma_rd, tag):
self.tag = tag

self.submodules.writer = FtdiDMAWriter(lasmim_ftdi_dma_wr)
self.submodules.reader = FtdiDMAReader(lasmim_ftdi_dma_rd, self.tag)
self.submodules.writer = LiteUSBDMAWriter(lasmim_ftdi_dma_wr)
self.submodules.reader = LiteUSBDMAReader(lasmim_ftdi_dma_rd, self.tag)
self.submodules.ev = SharedIRQ(self.writer.ev, self.reader.ev)

self.sink = self.writer.sink
4 changes: 2 additions & 2 deletions misoclib/com/liteusb/frontend/uart.py
Original file line number Diff line number Diff line change
@@ -3,9 +3,9 @@
from migen.bank.eventmanager import *
from migen.genlib.fifo import SyncFIFOBuffered

from liteusb.ftdi.std import *
from misoclib.com.liteusb.common import *

class FtdiUART(Module, AutoCSR):
class LiteUSBUART(Module, AutoCSR):
def __init__(self, tag, fifo_depth=64):
self.tag = tag

27 changes: 16 additions & 11 deletions misoclib/com/liteusb/phy/ft2232h.py
Original file line number Diff line number Diff line change
@@ -3,9 +3,9 @@
from migen.actorlib.fifo import AsyncFIFO
from migen.fhdl.specials import *

from liteusb.ftdi.std import *
from misoclib.com.liteusb.common import *

class FtdiPHY(Module):
class FT2232HPHY(Module):
def __init__(self, pads, fifo_depth=32, read_time=16, write_time=16):
dw = flen(pads.data)

@@ -100,22 +100,27 @@ def anti_starvation(timeout):
data_r = Signal(dw)
data_oe = Signal()

pads.oe_n.reset = 1
if hasattr(pads, "oe_n"):
pads_oe_n = pads.oe_n
else:
pads_oe_n = Signal()

pads_oe_n.reset = 1
pads.rd_n.reset = 1
pads.wr_n.reset = 1

self.sync.ftdi += [
If(fsm.ongoing("READ"),
data_oe.eq(0),

pads.oe_n.eq(0),
pads_oe_n.eq(0),
pads.rd_n.eq(~wants_read),
pads.wr_n.eq(1)

).Elif(fsm.ongoing("WRITE"),
data_oe.eq(1),

pads.oe_n.eq(1),
pads_oe_n.eq(1),
pads.rd_n.eq(1),
pads.wr_n.eq(~wants_write),

@@ -124,7 +129,7 @@ def anti_starvation(timeout):
).Else(
data_oe.eq(1),

pads.oe_n.eq(~fsm.ongoing("WTR")),
pads_oe_n.eq(~fsm.ongoing("WTR")),
pads.rd_n.eq(1),
pads.wr_n.eq(1)
),
@@ -147,7 +152,7 @@ def anti_starvation(timeout):
#
# TB
#
class FtdiModel(Module, RandRun):
class FT2232HModel(Module, RandRun):
def __init__(self, rd_data):
RandRun.__init__(self, 50)
self.rd_data = [0] + rd_data
@@ -253,8 +258,8 @@ def do_simulation(self, selfp):

class TB(Module):
def __init__(self):
self.submodules.model = FtdiModel(model_rd_data)
self.submodules.phy = FtdiPHY(self.model)
self.submodules.model = FT2232HModel(model_rd_data)
self.submodules.phy = FT2232HPHY(self.model)

self.submodules.user = UserModel(user_wr_data)

@@ -300,8 +305,8 @@ def main():
#print(len(tb.user.rd_data))
#print(len(tb.model.wr_data))

print_results("FtdiModel --> UserModel", model_rd_data, tb.user.rd_data)
print_results("UserModel --> FtdiModel", user_wr_data, tb.model.wr_data)
print_results("F2232HModel --> UserModel", model_rd_data, tb.user.rd_data)
print_results("UserModel --> FT2232HModel", user_wr_data, tb.model.wr_data)

if __name__ == "__main__":
main()