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  • 2 commits
  • 13 files changed
  • 1 contributor

Commits on Mar 21, 2015

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Showing with 42 additions and 42 deletions.
  1. +3 −3 make.py
  2. +12 −12 misoclib/soc/__init__.py
  3. +4 −4 misoclib/soc/sdram.py
  4. +7 −7 software/bios/boot.c
  5. +1 −1 software/bios/sdram.c
  6. +1 −1 software/libbase/system.c
  7. +2 −2 targets/de0nano.py
  8. +2 −2 targets/kc705.py
  9. +2 −2 targets/mlabs_video.py
  10. +3 −3 targets/pipistrello.py
  11. +2 −2 targets/ppro.py
  12. +2 −2 targets/simple.py
  13. +1 −1 targets/versa.py
6 changes: 3 additions & 3 deletions make.py
Original file line number Diff line number Diff line change
@@ -122,9 +122,9 @@ def _get_args():
actions["build-bios"] = True
if not actions["load-bitstream"]:
actions["flash-bitstream"] = True
if not soc.with_rom:
if not soc.with_integrated_rom:
actions["flash-bios"] = True
if actions["build-bitstream"] and soc.with_rom:
if actions["build-bitstream"] and soc.with_integrated_rom:
actions["build-bios"] = True
if actions["build-bios"]:
actions["build-headers"] = True
@@ -173,7 +173,7 @@ def _get_args():
raise OSError("BIOS build failed")

if actions["build-bitstream"]:
if soc.with_rom:
if soc.with_integrated_rom:
with open(soc.cpu_boot_file, "rb") as boot_file:
boot_data = []
while True:
24 changes: 12 additions & 12 deletions misoclib/soc/__init__.py
Original file line number Diff line number Diff line change
@@ -31,15 +31,15 @@ class SoC(Module):
mem_map = {
"rom": 0x00000000, # (shadow @0x80000000)
"sram": 0x10000000, # (shadow @0x90000000)
"sdram": 0x40000000, # (shadow @0xc0000000)
"main_ram": 0x40000000, # (shadow @0xc0000000)
"csr": 0x60000000, # (shadow @0xe0000000)
}
def __init__(self, platform, clk_freq, cpu_or_bridge=None,
with_cpu=True, cpu_type="lm32", cpu_reset_address=0x00000000,
cpu_boot_file="software/bios/bios.bin",
with_rom=False, rom_size=0x8000,
with_sram=True, sram_size=4096,
with_main_ram=False, main_ram_size=64*1024,
with_integrated_rom=False, rom_size=0x8000,
with_integrated_sram=True, sram_size=4096,
with_integrated_main_ram=False, main_ram_size=64*1024,
with_csr=True, csr_data_width=8, csr_address_width=14,
with_uart=True, uart_baudrate=115200,
with_identifier=True,
@@ -50,19 +50,19 @@ def __init__(self, platform, clk_freq, cpu_or_bridge=None,

self.with_cpu = with_cpu
self.cpu_type = cpu_type
if with_rom:
if with_integrated_rom:
self.cpu_reset_address = 0
else:
self.cpu_reset_address = cpu_reset_address
self.cpu_boot_file = cpu_boot_file

self.with_rom = with_rom
self.with_integrated_rom = with_integrated_rom
self.rom_size = rom_size

self.with_sram = with_sram
self.with_integrated_sram = with_integrated_sram
self.sram_size = sram_size

self.with_main_ram = with_main_ram
self.with_integrated_main_ram = with_integrated_main_ram
self.main_ram_size = main_ram_size

self.with_uart = with_uart
@@ -90,18 +90,18 @@ def __init__(self, platform, clk_freq, cpu_or_bridge=None,
self.cpu_or_bridge = self.cpu
self._wb_masters += [self.cpu.ibus, self.cpu.dbus]

if with_rom:
if with_integrated_rom:
self.submodules.rom = wishbone.SRAM(rom_size, read_only=True)
self.register_rom(self.rom.bus, rom_size)

if with_sram:
if with_integrated_sram:
self.submodules.sram = wishbone.SRAM(sram_size)
self.register_mem("sram", self.mem_map["sram"], self.sram.bus, sram_size)

# Note: Main Ram can be used when no external SDRAM is available and use SDRAM mapping.
if with_main_ram:
if with_integrated_main_ram:
self.submodules.main_ram = wishbone.SRAM(main_ram_size)
self.register_mem("sdram", self.mem_map["sdram"], self.main_ram.bus, main_ram_size)
self.register_mem("main_ram", self.mem_map["main_ram"], self.main_ram.bus, main_ram_size)

elif cpu_or_bridge is not None and not isinstance(cpu_or_bridge, CPU):
self._wb_masters += [cpu_or_bridge.wishbone]
8 changes: 4 additions & 4 deletions misoclib/soc/sdram.py
Original file line number Diff line number Diff line change
@@ -63,24 +63,24 @@ def register_sdram_phy(self, phy, geom_settings, timing_settings, controller_set
self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_size//4, self.sdram.crossbar.get_master())
lasmic = self.sdram.controller.lasmic
main_ram_size = 2**lasmic.aw*lasmic.dw*lasmic.nbanks//8
self.register_mem("sdram", self.mem_map["sdram"], self.wishbone2lasmi.wishbone, main_ram_size)
self.register_mem("main_ram", self.mem_map["main_ram"], self.wishbone2lasmi.wishbone, main_ram_size)

# MINICON frontend
elif self.ramcon_type == "minicon":
sdram_width = flen(self.sdram.controller.bus.dat_r)
main_ram_size = 2**(geom_settings.bank_a+geom_settings.row_a+geom_settings.col_a)*sdram_width//8

if sdram_width == 32:
self.register_mem("sdram", self.mem_map["sdram"], self.sdram.controller.bus, main_ram_size)
self.register_mem("main_ram", self.mem_map["main_ram"], self.sdram.controller.bus, main_ram_size)
elif sdram_width < 32:
self.submodules.downconverter = downconverter = wishbone.DownConverter(32, sdram_width)
self.comb += Record.connect(downconverter.wishbone_o, self.sdram.controller.bus)
self.register_mem("sdram", self.mem_map["sdram"], downconverter.wishbone_i, main_ram_size)
self.register_mem("main_ram", self.mem_map["main_ram"], downconverter.wishbone_i, main_ram_size)
else:
raise NotImplementedError("Unsupported SDRAM width of {} > 32".format(sdram_width))

def do_finalize(self):
if not self.with_main_ram:
if not self.with_integrated_main_ram:
if not self._sdram_phy_registered:
raise FinalizeError("Need to call SDRAMSoC.register_sdram_phy()")
SoC.do_finalize(self)
14 changes: 7 additions & 7 deletions software/bios/boot.c
Original file line number Diff line number Diff line change
@@ -215,20 +215,20 @@ void netboot(void)

microudp_start(macadr, IPTOINT(LOCALIP1, LOCALIP2, LOCALIP3, LOCALIP4));

if(tftp_get_v(ip, "boot.bin", (void *)SDRAM_BASE) <= 0) {
if(tftp_get_v(ip, "boot.bin", (void *)MAIN_RAM_BASE) <= 0) {
printf("Network boot failed\n");
return;
}

cmdline_adr = SDRAM_BASE+0x1000000;
cmdline_adr = MAIN_RAM_BASE+0x1000000;
size = tftp_get_v(ip, "cmdline.txt", (void *)cmdline_adr);
if(size <= 0) {
printf("No command line parameters found\n");
cmdline_adr = 0;
} else
*((char *)(cmdline_adr+size)) = 0x00;

initrdstart_adr = SDRAM_BASE+0x1002000;
initrdstart_adr = MAIN_RAM_BASE+0x1002000;
size = tftp_get_v(ip, "initrd.bin", (void *)initrdstart_adr);
if(size <= 0) {
printf("No initial ramdisk found\n");
@@ -237,7 +237,7 @@ void netboot(void)
} else
initrdend_adr = initrdstart_adr + size;

boot(cmdline_adr, initrdstart_adr, initrdend_adr, SDRAM_BASE);
boot(cmdline_adr, initrdstart_adr, initrdend_adr, MAIN_RAM_BASE);
}

#endif
@@ -260,12 +260,12 @@ void flashboot(void)
}

printf("Loading %d bytes from flash...\n", length);
memcpy((void *)SDRAM_BASE, flashbase, length);
got_crc = crc32((unsigned char *)SDRAM_BASE, length);
memcpy((void *)MAIN_RAM_BASE, flashbase, length);
got_crc = crc32((unsigned char *)MAIN_RAM_BASE, length);
if(crc != got_crc) {
printf("CRC failed (expected %08x, got %08x)\n", crc, got_crc);
return;
}
boot(0, 0, 0, SDRAM_BASE);
boot(0, 0, 0, MAIN_RAM_BASE);
}
#endif
2 changes: 1 addition & 1 deletion software/bios/sdram.c
Original file line number Diff line number Diff line change
@@ -429,7 +429,7 @@ int sdrlevel(void)

int memtest_silent(void)
{
volatile unsigned int *array = (unsigned int *)SDRAM_BASE;
volatile unsigned int *array = (unsigned int *)MAIN_RAM_BASE;
int i;
unsigned int prv;
unsigned int error_cnt;
2 changes: 1 addition & 1 deletion software/libbase/system.c
Original file line number Diff line number Diff line change
@@ -77,7 +77,7 @@ void flush_l2_cache(void)

l2_nwords = 1 << wishbone2lasmi_cachesize_read();
for(i=0;i<2*l2_nwords;i++) {
addr = SDRAM_BASE + i*4;
addr = MAIN_RAM_BASE + i*4;
#ifdef __lm32__
__asm__ volatile("lw %0, (%1+0)\n":"=r"(dummy):"r"(addr));
#else
4 changes: 2 additions & 2 deletions targets/de0nano.py
Original file line number Diff line number Diff line change
@@ -85,12 +85,12 @@ class BaseSoC(SDRAMSoC):
def __init__(self, platform, **kwargs):
SDRAMSoC.__init__(self, platform,
clk_freq=100*1000000,
with_rom=True,
with_integrated_rom=True,
**kwargs)

self.submodules.crg = _CRG(platform)

if not self.with_main_ram:
if not self.with_integrated_main_ram:
sdram_module = IS42S16160(self.clk_freq)
sdram_controller_settings = sdram.ControllerSettings(
req_queue_size=8,
4 changes: 2 additions & 2 deletions targets/kc705.py
Original file line number Diff line number Diff line change
@@ -83,7 +83,7 @@ def __init__(self, platform, **kwargs):

self.submodules.crg = _CRG(platform)

if not self.with_main_ram:
if not self.with_integrated_main_ram:
sdram_modules = MT8JTF12864(self.clk_freq)
sdram_controller_settings = sdram.ControllerSettings(
req_queue_size=8,
@@ -103,7 +103,7 @@ def __init__(self, platform, **kwargs):
self.flash_boot_address = 0xb00000

# If not in ROM, BIOS is in SPI flash
if not self.with_rom:
if not self.with_integrated_rom:
self.register_rom(self.spiflash.bus)

class MiniSoC(BaseSoC):
4 changes: 2 additions & 2 deletions targets/mlabs_video.py
Original file line number Diff line number Diff line change
@@ -41,7 +41,7 @@ def __init__(self, platform, **kwargs):

self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq)

if not self.with_main_ram:
if not self.with_integrated_main_ram:
sdram_modules = MT46V32M16(self.clk_freq)
sdram_controller_settings = sdram.ControllerSettings(
req_queue_size=8,
@@ -64,7 +64,7 @@ def __init__(self, platform, **kwargs):
self.flash_boot_address = 0x001a0000

# If not in ROM, BIOS is in // NOR flash
if not self.with_rom:
if not self.with_integrated_rom:
self.register_rom(self.norflash.bus)


6 changes: 3 additions & 3 deletions targets/pipistrello.py
Original file line number Diff line number Diff line change
@@ -91,14 +91,14 @@ class BaseSoC(SDRAMSoC):

def __init__(self, platform, **kwargs):
clk_freq = 75*1000*1000
if not kwargs.get("with_rom"):
if not kwargs.get("with_integrated_rom"):
kwargs["rom_size"] = 0x1000000 # 128 Mb
SDRAMSoC.__init__(self, platform, clk_freq,
cpu_reset_address=0x170000, **kwargs) # 1.5 MB

self.submodules.crg = _CRG(platform, clk_freq)

if not self.with_main_ram:
if not self.with_integrated_main_ram:
sdram_module = MT46H32M16(self.clk_freq)
sdram_controller_settings = sdram.ControllerSettings(
req_queue_size=8,
@@ -119,7 +119,7 @@ def __init__(self, platform, **kwargs):

self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash4x"), dummy=10, div=4)
# If not in ROM, BIOS is in SPI flash
if not self.with_rom:
if not self.with_integrated_rom:
self.flash_boot_address = 0x180000
self.register_rom(self.spiflash.bus)

4 changes: 2 additions & 2 deletions targets/ppro.py
Original file line number Diff line number Diff line change
@@ -74,7 +74,7 @@ def __init__(self, platform, **kwargs):

self.submodules.crg = _CRG(platform, clk_freq)

if not self.with_main_ram:
if not self.with_integrated_main_ram:
sdram_module = MT48LC4M16(clk_freq)
sdram_controller_settings = sdram.ControllerSettings(
req_queue_size=8,
@@ -89,7 +89,7 @@ def __init__(self, platform, **kwargs):
self.flash_boot_address = 0x70000

# If not in ROM, BIOS is in SPI flash
if not self.with_rom:
if not self.with_integrated_rom:
self.register_rom(self.spiflash.bus)

default_subtarget = BaseSoC
4 changes: 2 additions & 2 deletions targets/simple.py
Original file line number Diff line number Diff line change
@@ -10,8 +10,8 @@ class BaseSoC(SoC):
def __init__(self, platform, **kwargs):
SoC.__init__(self, platform,
clk_freq=int((1/(platform.default_clk_period))*1000000000),
with_rom=True,
with_main_ram=True, main_ram_size=16*1024,
with_integrated_rom=True,
with_integrated_main_ram=True, main_ram_size=16*1024,
**kwargs)
self.submodules.crg = CRG(platform.request(platform.default_clk_name))

2 changes: 1 addition & 1 deletion targets/versa.py
Original file line number Diff line number Diff line change
@@ -9,7 +9,7 @@ class BaseSoC(SoC):
def __init__(self, platform, **kwargs):
SoC.__init__(self, platform,
clk_freq=100*1000000,
with_rom=True,
with_integrated_rom=True,
**kwargs)
self.submodules.crg = CRG(platform.request("clk100"), ~platform.request("rst_n"))
self.comb += platform.request("user_led", 0).eq(ResetSignal())