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base repository: m-labs/misoc
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head repository: m-labs/misoc
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compare: b75e4b237df5
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Mar 21, 2015

  1. Copy the full SHA
    c60d995 View commit details
  2. software/bios/memtest: add data bus test (0xAAAAAAAA, 0x55555555) on …

    …a small portion of the test zone.
    
    we now need to add another random addressing test to avoid linear access on L2 cache
    enjoy-digital committed Mar 21, 2015
    Copy the full SHA
    b75e4b2 View commit details
Showing with 19 additions and 4 deletions.
  1. +1 −0 misoclib/mem/sdram/module.py
  2. +18 −4 software/bios/sdram.c
1 change: 1 addition & 0 deletions misoclib/mem/sdram/module.py
Original file line number Diff line number Diff line change
@@ -13,6 +13,7 @@
# configurations.
# - Modules can have different speedgrades, add support for it (and also add
# a check to verify clk_freq is in the supported range)
# Try to uniformize tREFI computations between modules

from math import ceil

22 changes: 18 additions & 4 deletions software/bios/sdram.c
Original file line number Diff line number Diff line change
@@ -424,22 +424,36 @@ int sdrlevel(void)

#define TEST_SIZE (2*1024*1024)

#define ONEZERO 0xAAAAAAAA
#define ZEROONE 0x55555555

int memtest_silent(void)
{
volatile unsigned int *array = (unsigned int *)SDRAM_BASE;
int i;
unsigned int prv;
unsigned int error_cnt;

for(i=0;i<TEST_SIZE/4;i++) {
array[i] = 0x5A5A5A5A;
/* test data bus */
for(i=0;i<128;i++) {
array[i] = ONEZERO;
}
error_cnt = 0;
for(i=0;i<TEST_SIZE/4;i++) {
if(array[i] != 0x5A5A5A5A)
for(i=0;i<128;i++) {
if(array[i] != ONEZERO)
error_cnt++;
}

for(i=0;i<128;i++) {
array[i] = ZEROONE;
}
error_cnt = 0;
for(i=0;i<128;i++) {
if(array[i] != ZEROONE)
error_cnt++;
}

/* test random data */
prv = 0;
for(i=0;i<TEST_SIZE/4;i++) {
prv = 1664525*prv + 1013904223;