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base repository: m-labs/misoc
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head repository: m-labs/misoc
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compare: 45eb5090dba3
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  • 2 commits
  • 1 file changed
  • 1 contributor

Commits on Mar 21, 2015

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    a560ba3 View commit details
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    45eb509 View commit details
Showing with 20 additions and 0 deletions.
  1. +20 −0 misoclib/mem/sdram/module.py
20 changes: 20 additions & 0 deletions misoclib/mem/sdram/module.py
Original file line number Diff line number Diff line change
@@ -49,6 +49,7 @@ class IS42S16160(SDRAMModule):
"nrows": 8192,
"ncols": 512
}
# Note: timings for -7 speedgrade (add support for others speedgrades)
timing_settings = {
"tRP": 20,
"tRCD": 20,
@@ -79,6 +80,25 @@ def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, self.geom_settings,
self.timing_settings)

class AS4C16M16(SDRAMModule):
geom_settings = {
"nbanks": 4,
"nrows": 8192,
"ncols": 512
}
# Note: timings for -6 speedgrade (add support for others speedgrades)
timing_settings = {
"tRP": 18,
"tRCD": 18,
"tWR": 12,
"tWTR": 2,
"tREFI": 256*1000*1000/4096,
"tRFC": 60
}
def __init__(self, clk_freq):
SDRAMModule.__init__(self, clk_freq, self.geom_settings,
self.timing_settings)

# DDR
class MT46V32M16(SDRAMModule):
geom_settings = {