sdram/module: add MT47H128M8 DDR2 (used for a customer)

m-labs · Mar 21, 2015 · 0f9b0c6 · 0f9b0c6
1 parent 45eb509
commit 0f9b0c6
Showing 1 changed file with 17 additions and 0 deletions.
diff --git a/misoclib/mem/sdram/module.py b/misoclib/mem/sdram/module.py
@@ -138,6 +138,23 @@ def __init__(self, clk_freq):
 			self.timing_settings)
 
 # DDR2
+class MT47H128M8(SDRAMModule):
+	geom_settings = {
+		"nbanks":	8,
+		"nrows":	16384,
+		"ncols":	1024
+	}
+	timing_settings = {
+		"tRP":		15,
+		"tRCD":		15,
+		"tWR":		15,
+		"tWTR":		2,
+		"tREFI":	7800,
+		"tRFC":		127.5
+	}
+	def __init__(self, clk_freq):
+		SDRAMModule.__init__(self, clk_freq, self.geom_settings,
+			self.timing_settings)
 
 # DDR3
 class MT8JTF12864(SDRAMModule):