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base repository: m-labs/migen
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head repository: m-labs/migen
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compare: d6041879dd42
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  • 2 commits
  • 10 files changed
  • 1 contributor

Commits on Mar 16, 2015

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    e903b62 View commit details
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    d604187 View commit details
2 changes: 2 additions & 0 deletions mibuild/altera/__init__.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,2 @@
from mibuild.altera.platform import AlteraPlatform
from mibuild.altera.programmer import USBBlaster
1 change: 1 addition & 0 deletions mibuild/altera/common.py
Original file line number Diff line number Diff line change
@@ -0,0 +1 @@
altera_special_overrides = {}
25 changes: 25 additions & 0 deletions mibuild/altera/platform.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,25 @@
from mibuild.generic_platform import GenericPlatform
from mibuild.altera import common, quartus

class AlteraPlatform(GenericPlatform):
bitstream_ext = ".sof"

def __init__(self, *args, toolchain="quartus", **kwargs):
GenericPlatform.__init__(self, *args, **kwargs)
if toolchain == "quartus":
self.toolchain = quartus.AlteraQuartusToolchain()
else:
raise ValueError("Unknown toolchain")

def get_verilog(self, *args, special_overrides=dict(), **kwargs):
so = dict(common.altera_special_overrides)
so.update(special_overrides)
return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs)

def build(self, *args, **kwargs):
return self.toolchain.build(self, *args, **kwargs)

def add_period_constraint(self, clk, period):
if hasattr(clk, "p"):
clk = clk.p
self.toolchain.add_period_constraint(self, clk, period)
23 changes: 12 additions & 11 deletions mibuild/altera/quartus.py
Original file line number Diff line number Diff line change
@@ -5,7 +5,9 @@

from migen.fhdl.structure import _Fragment
from mibuild.generic_platform import *

from mibuild import tools
from mibuild.xilinx import common

def _format_constraint(c):
if isinstance(c, Pins):
@@ -69,31 +71,30 @@ def _run_quartus(build_name, quartus_path):
if r != 0:
raise OSError("Subprocess failed")

class AlteraQuartusPlatform(GenericPlatform):
bitstream_ext = ".sof"
def build(self, fragment, build_dir="build", build_name="top",
class AlteraQuartusToolchain:
def build(self, platform, fragment, build_dir="build", build_name="top",
quartus_path="/opt/Altera", run=True):
tools.mkdir_noerror(build_dir)
os.chdir(build_dir)

if not isinstance(fragment, _Fragment):
fragment = fragment.get_fragment()
self.finalize(fragment)
platform.finalize(fragment)

v_src, vns = self.get_verilog(fragment)
named_sc, named_pc = self.resolve_signals(vns)
v_src, vns = platform.get_verilog(fragment)
named_sc, named_pc = platform.resolve_signals(vns)
v_file = build_name + ".v"
tools.write_to_file(v_file, v_src)
sources = self.sources + [(v_file, "verilog")]
_build_files(self.device, sources, self.verilog_include_paths, named_sc, named_pc, build_name)
sources = platform.sources + [(v_file, "verilog")]
_build_files(platform.device, sources, platform.verilog_include_paths, named_sc, named_pc, build_name)
if run:
_run_quartus(build_name, quartus_path)

os.chdir("..")

return vns

def add_period_constraint(self, clk, period):
def add_period_constraint(self, platform, clk, period):
# TODO: handle differential clk
self.add_platform_command("""set_global_assignment -name DUTY_CYCLE 50 -section_id {clk}""", clk=clk)
self.add_platform_command("""set_global_assignment -name FMAX_REQUIREMENT "{freq} MHz" -section_id {clk}\n""".format(freq=str(float(1/period)*1000), clk="{clk}"), clk=clk)
platform.add_platform_command("""set_global_assignment -name DUTY_CYCLE 50 -section_id {clk}""", clk=clk)
platform.add_platform_command("""set_global_assignment -name FMAX_REQUIREMENT "{freq} MHz" -section_id {clk}\n""".format(freq=str(float(1/period)*1000), clk="{clk}"), clk=clk)
2 changes: 2 additions & 0 deletions mibuild/lattice/__init__.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,2 @@
from mibuild.lattice.platform import LatticePlatform
from mibuild.lattice.programmer import LatticeProgrammer
1 change: 1 addition & 0 deletions mibuild/lattice/common.py
Original file line number Diff line number Diff line change
@@ -0,0 +1 @@
lattice_special_overrides = {}
21 changes: 11 additions & 10 deletions mibuild/lattice/diamond.py
Original file line number Diff line number Diff line change
@@ -5,7 +5,9 @@

from migen.fhdl.structure import _Fragment
from mibuild.generic_platform import *

from mibuild import tools
from mibuild.lattice import common

def _format_constraint(c):
if isinstance(c, Pins):
@@ -61,23 +63,22 @@ def _run_diamond(build_name, source, ver=None):
if r != 0:
raise OSError("Subprocess failed")

class LatticeDiamondPlatform(GenericPlatform):
bitstream_ext = ".bit"
def build(self, fragment, build_dir="build", build_name="top",
class LatticeDiamondToolchain:
def build(self, platform, fragment, build_dir="build", build_name="top",
diamond_path="/opt/Diamond", run=True):
tools.mkdir_noerror(build_dir)
os.chdir(build_dir)

if not isinstance(fragment, _Fragment):
fragment = fragment.get_fragment()
self.finalize(fragment)
platform.finalize(fragment)

v_src, vns = self.get_verilog(fragment)
named_sc, named_pc = self.resolve_signals(vns)
v_src, vns = platform.get_verilog(fragment)
named_sc, named_pc = platform.resolve_signals(vns)
v_file = build_name + ".v"
tools.write_to_file(v_file, v_src)
sources = self.sources + [(v_file, "verilog")]
_build_files(self.device, sources, self.verilog_include_paths, build_name)
sources = platform.sources + [(v_file, "verilog")]
_build_files(platform.device, sources, platform.verilog_include_paths, build_name)

tools.write_to_file(build_name + ".lpf", _build_lpf(named_sc, named_pc))

@@ -88,6 +89,6 @@ def build(self, fragment, build_dir="build", build_name="top",

return vns

def add_period_constraint(self, clk, period):
def add_period_constraint(self, platform, clk, period):
# TODO: handle differential clk
self.add_platform_command("""FREQUENCY PORT "{clk}" {freq} MHz;""".format(freq=str(float(1/period)*1000), clk="{clk}"), clk=clk)
platform.add_platform_command("""FREQUENCY PORT "{clk}" {freq} MHz;""".format(freq=str(float(1/period)*1000), clk="{clk}"), clk=clk)
25 changes: 25 additions & 0 deletions mibuild/lattice/platform.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,25 @@
from mibuild.generic_platform import GenericPlatform
from mibuild.lattice import common, diamond

class LatticePlatform(GenericPlatform):
bitstream_ext = ".bit"

def __init__(self, *args, toolchain="diamond", **kwargs):
GenericPlatform.__init__(self, *args, **kwargs)
if toolchain == "diamond":
self.toolchain = diamond.LatticeDiamondToolchain()
else:
raise ValueError("Unknown toolchain")

def get_verilog(self, *args, special_overrides=dict(), **kwargs):
so = dict(common.lattice_special_overrides)
so.update(special_overrides)
return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs)

def build(self, *args, **kwargs):
return self.toolchain.build(self, *args, **kwargs)

def add_period_constraint(self, clk, period):
if hasattr(clk, "p"):
clk = clk.p
self.toolchain.add_period_constraint(self, clk, period)
6 changes: 3 additions & 3 deletions mibuild/platforms/de0nano.py
Original file line number Diff line number Diff line change
@@ -2,7 +2,7 @@
# License: BSD

from mibuild.generic_platform import *
from mibuild.altera.quartus import AlteraQuartusPlatform
from mibuild.altera import AlteraPlatform
from mibuild.altera.programmer import USBBlaster

_io = [
@@ -90,12 +90,12 @@
),
]

class Platform(AlteraQuartusPlatform):
class Platform(AlteraPlatform):
default_clk_name = "clk50"
default_clk_period = 20

def __init__(self):
AlteraQuartusPlatform.__init__(self, "EP4CE22F17C6", _io)
AlteraPlatform.__init__(self, "EP4CE22F17C6", _io)

def create_programmer(self):
return USBBlaster()
6 changes: 3 additions & 3 deletions mibuild/platforms/versa.py
Original file line number Diff line number Diff line change
@@ -2,7 +2,7 @@
# License: BSD

from mibuild.generic_platform import *
from mibuild.lattice.diamond import LatticeDiamondPlatform
from mibuild.lattice import LatticePlatform
from mibuild.lattice.programmer import LatticeProgrammer

_io = [
@@ -23,12 +23,12 @@
),
]

class Platform(LatticeDiamondPlatform):
class Platform(LatticePlatform):
default_clk_name = "clk100"
default_clk_period = 10

def __init__(self):
LatticeDiamondPlatform.__init__(self, "LFE3-35EA-6FN484C", _io)
LatticePlatform.__init__(self, "LFE3-35EA-6FN484C", _io)

def create_programmer(self):
return LatticeProgrammer()