Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: m-labs/migen
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: b3b1209c62b0
Choose a base ref
...
head repository: m-labs/migen
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: b5a9909b0899
Choose a head ref
  • 3 commits
  • 3 files changed
  • 1 contributor

Commits on Mar 16, 2015

  1. Copy the full SHA
    69ce6dd View commit details
  2. Copy the full SHA
    993059a View commit details
  3. Copy the full SHA
    b5a9909 View commit details
Showing with 69 additions and 1 deletion.
  1. +18 −1 mibuild/lattice/common.py
  2. +14 −0 mibuild/xilinx/common.py
  3. +37 −0 migen/genlib/io.py
19 changes: 18 additions & 1 deletion mibuild/lattice/common.py
Original file line number Diff line number Diff line change
@@ -1 +1,18 @@
lattice_special_overrides = {}
from migen.fhdl.std import *
from migen.genlib.io import *

class LatticeDifferentialOutput:
@staticmethod
def lower(dr):
return LatticeDifferentialOutputImpl(dr.i, dr.o_p, dr.o_n)

class LatticeDDROutputImpl(Module):
def __init__(self, i1, i2, o, clk):
self.specials += Instance("ODDRA",
i_CLK=clk, i_RST=0,
i_DA=i1, i_DB=i2, o_Q=o,
)

lattice_special_overrides = {
DDROutput: LatticeDDROutput
}
14 changes: 14 additions & 0 deletions mibuild/xilinx/common.py
Original file line number Diff line number Diff line change
@@ -84,10 +84,24 @@ class XilinxDifferentialOutput:
def lower(dr):
return XilinxDifferentialOutputImpl(dr.i, dr.o_p, dr.o_n)

class XilinxDDROutputImpl(Module):
def __init__(self, i1, i2, o, clk):
self.specials += Instance("ODDR",
p_DDR_CLK_EDGE="SAME_EDGE",
i_C=clk, i_CE=1, i_S=0, i_R=0,
i_D1=i1, i_D2=i2, o_Q=o,
)

class XilinxDDROutput:
@staticmethod
def lower(dr):
return XilinxDDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk)

xilinx_special_overrides = {
NoRetiming: XilinxNoRetiming,
MultiReg: XilinxMultiReg,
AsyncResetSynchronizer: XilinxAsyncResetSynchronizer,
DifferentialInput: XilinxDifferentialInput,
DifferentialOutput: XilinxDifferentialOutput,
DDROutput: XilinxDDROutput
}
37 changes: 37 additions & 0 deletions migen/genlib/io.py
Original file line number Diff line number Diff line change
@@ -52,3 +52,40 @@ def __init__(self, clk):
self.cd_por.clk.eq(clk),
self.cd_sys.rst.eq(~rst_n)
]

class DDRInput(Special):
def __init__(self, i, o1, o2, clk=ClockSignal()):
Special.__init__(self)
self.i = i
self.o1 = o1
self.o2 = o2
self.clk = clk

def iter_expressions(self):
yield self, "i", SPECIAL_INPUT
yield self, "o1", SPECIAL_OUTPUT
yield self, "o2", SPECIAL_OUTPUT
yield self, "clk", SPECIAL_INPUT

@staticmethod
def lower(dr):
raise NotImplementedError("Attempted to use a DDR input, but platform does not support them")

class DDROutput(Special):
def __init__(self, i1, i2, o, clk=ClockSignal()):
Special.__init__(self)
self.i1 = i1
self.i2 = i2
self.o = o
self.clk = clk

def iter_expressions(self):
yield self, "i1", SPECIAL_INPUT
yield self, "i2", SPECIAL_INPUT
yield self, "o", SPECIAL_OUTPUT
yield self, "clk", SPECIAL_INPUT

@staticmethod
def lower(dr):
raise NotImplementedError("Attempted to use a DDR output, but platform does not support them")