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base repository: m-labs/misoc
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head repository: m-labs/misoc
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compare: 82fe83a1c494
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Mar 19, 2015

  1. Copy the full SHA
    9f2e5cd View commit details
  2. sdram: raise NotImplementedError if Minicon is used others memories t…

    …han SDR (not functional for now)
    enjoy-digital committed Mar 19, 2015
    2
    Copy the full SHA
    82fe83a View commit details
Showing with 6 additions and 2 deletions.
  1. +2 −0 misoclib/soc/sdram.py
  2. +4 −2 targets/kc705.py
2 changes: 2 additions & 0 deletions misoclib/soc/sdram.py
Original file line number Diff line number Diff line change
@@ -36,6 +36,8 @@ def register_sdram_phy(self, phy, sdram_geom, sdram_timing):
if self._sdram_phy_registered:
raise FinalizeError
self._sdram_phy_registered = True
if self.ramcon_type == "minicon" and phy.settings.memtype != "SDR":
raise NotImplementedError("Minicon only supports SDR memtype for now (" + phy.settings.memtype + ")")

# Core
self.submodules.sdram = SDRAMCore(phy, self.ramcon_type, sdram_geom, sdram_timing)
6 changes: 4 additions & 2 deletions targets/kc705.py
Original file line number Diff line number Diff line change
@@ -20,6 +20,8 @@ def __init__(self, platform):
clk200_se = Signal()
self.specials += Instance("IBUFDS", i_I=clk200.p, i_IB=clk200.n, o_O=clk200_se)

rst = platform.request("cpu_reset")

pll_locked = Signal()
pll_fb = Signal()
self.pll_sys = Signal()
@@ -50,8 +52,8 @@ def __init__(self, platform):
Instance("BUFG", i_I=self.pll_sys, o_O=self.cd_sys.clk),
Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),
AsyncResetSynchronizer(self.cd_sys, ~pll_locked),
AsyncResetSynchronizer(self.cd_clk200, ~pll_locked),
AsyncResetSynchronizer(self.cd_sys, ~pll_locked | rst),
AsyncResetSynchronizer(self.cd_clk200, ~pll_locked | rst),
]

reset_counter = Signal(4, reset=15)