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enjoy-digitalenjoy-digital
committedMar 21, 2015
sdram: pass sdram_controller_settings to SDRAMSoC
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0.120.1
1 parent 70469e1 commit 30c2521

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9 files changed

+57
-44
lines changed

9 files changed

+57
-44
lines changed
 

Diff for: ‎misoclib/mem/sdram/core/__init__.py

+3-7
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,3 @@
1-
from collections import namedtuple
2-
31
from migen.fhdl.std import *
42
from migen.genlib.record import *
53
from migen.bank.description import *
@@ -8,8 +6,6 @@
86
from misoclib.mem.sdram.core import minicon, lasmicon
97
from misoclib.mem.sdram.core import lasmixbar
108

11-
ControllerSettings = namedtuple("ControllerSettings", "type req_queue_size read_time write_time")
12-
139
class SDRAMCore(Module, AutoCSR):
1410
def __init__(self, phy, geom_settings, timing_settings, controller_settings, **kwargs):
1511
# DFI
@@ -18,16 +14,16 @@ def __init__(self, phy, geom_settings, timing_settings, controller_settings, **k
1814
self.comb += Record.connect(self.dfii.master, phy.dfi)
1915

2016
# LASMICON
21-
if controller_settings.type == "lasmicon":
17+
if isinstance(controller_settings, lasmicon.LASMIconSettings):
2218
self.submodules.controller = controller = lasmicon.LASMIcon(phy.settings, geom_settings, timing_settings,
2319
controller_settings, **kwargs)
2420
self.comb += Record.connect(controller.dfi, self.dfii.slave)
2521

2622
self.submodules.crossbar = crossbar = lasmixbar.LASMIxbar([controller.lasmic], controller.nrowbits)
2723

2824
# MINICON
29-
elif controller_settings.type == "minicon":
25+
elif isinstance(controller_settings, minicon.MiniconSettings):
3026
self.submodules.controller = controller = minicon.Minicon(phy.settings, geom_settings, timing_settings)
3127
self.comb += Record.connect(controller.dfi, self.dfii.slave)
3228
else:
33-
raise ValueError("Unsupported SDRAM controller type: {}".format(controller_settings.type))
29+
raise ValueError("Unsupported SDRAM controller type")

Diff for: ‎misoclib/mem/sdram/core/lasmicon/__init__.py

+14
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,20 @@
66
from misoclib.mem.sdram.core.lasmicon.bankmachine import *
77
from misoclib.mem.sdram.core.lasmicon.multiplexer import *
88

9+
class LASMIconSettings:
10+
def __init__(self, req_queue_size=8,
11+
read_time=32, write_time=16,
12+
with_l2=True, l2_size=8192,
13+
with_bandwidth=False,
14+
with_memtest=False):
15+
self.req_queue_size = req_queue_size
16+
self.read_time = read_time
17+
self.write_time = write_time
18+
self.with_l2 = with_l2
Has conversations. Original line has conversations.
19+
self.l2_size = l2_size
20+
self.with_bandwidth = with_bandwidth
21+
self.with_memtest = with_memtest
22+
923
class LASMIcon(Module):
1024
def __init__(self, phy_settings, geom_settings, timing_settings, controller_settings, **kwargs):
1125
if phy_settings.memtype in ["SDR"]:

Diff for: ‎misoclib/mem/sdram/core/minicon/__init__.py

+4
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,10 @@ def col(self, address):
3434
else:
3535
return Cat(Replicate(0, self.address_align), address[:split])
3636

37+
class MiniconSettings:
38+
def __init__(self):
39+
pass
40+
3741
class Minicon(Module):
3842
def __init__(self, phy_settings, geom_settings, timing_settings):
3943
if phy_settings.memtype in ["SDR"]:

Diff for: ‎misoclib/soc/sdram.py

+17-30
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,9 @@
22
from migen.bus import wishbone, csr
33
from migen.genlib.record import *
44

5-
from misoclib.mem.sdram.core import ControllerSettings, SDRAMCore
5+
from misoclib.mem.sdram.core import SDRAMCore
6+
from misoclib.mem.sdram.core.lasmicon import LASMIconSettings
7+
from misoclib.mem.sdram.core.minicon import MiniconSettings
68
from misoclib.mem.sdram.frontend import memtest, wishbone2lasmi
79
from misoclib.soc import SoC, mem_decoder
810

@@ -15,66 +17,51 @@ class SDRAMSoC(SoC):
1517
}
1618
csr_map.update(SoC.csr_map)
1719

18-
def __init__(self, platform, clk_freq,
19-
sdram_controller_type="lasmicon", sdram_controller_req_queue_size=8,
20-
sdram_controller_read_time=32, sdram_controller_write_time=16,
21-
with_l2=True, l2_size=8192,
22-
with_bandwidth=False, # specific to LASMICON,
23-
with_memtest=False, # ignored for MINICON
20+
def __init__(self, platform, clk_freq, sdram_controller_settings,
2421
**kwargs):
2522
SoC.__init__(self, platform, clk_freq, **kwargs)
26-
self.sdram_controller_type = sdram_controller_type
27-
self.sdram_controller_settings = ControllerSettings(
28-
type=sdram_controller_type,
29-
# Below parameters are only used by LASMIcon
30-
req_queue_size=sdram_controller_req_queue_size,
31-
read_time=sdram_controller_read_time,
32-
write_time=sdram_controller_write_time
33-
)
34-
35-
self.with_l2 = with_l2
36-
self.l2_size = l2_size
37-
38-
self.with_memtest = with_memtest
39-
self.with_bandwidth = with_bandwidth or with_memtest
40-
23+
if isinstance(sdram_controller_settings, str):
24+
self.sdram_controller_settings = eval(sdram_controller_settings)
25+
else:
26+
self.sdram_controller_settings = sdram_controller_settings
4127
self._sdram_phy_registered = False
4228

4329
def register_sdram_phy(self, phy, geom_settings, timing_settings):
4430
if self._sdram_phy_registered:
4531
raise FinalizeError
4632
self._sdram_phy_registered = True
47-
if self.sdram_controller_type == "minicon" and phy.settings.memtype != "SDR":
33+
if isinstance(self.sdram_controller_settings, MiniconSettings) and phy.settings.memtype != "SDR":
4834
raise NotImplementedError("Minicon only supports SDR memtype for now (" + phy.settings.memtype + ")")
4935

5036
# Core
5137
self.submodules.sdram = SDRAMCore(phy, geom_settings, timing_settings, self.sdram_controller_settings)
5238

5339
# LASMICON frontend
54-
if self.sdram_controller_type == "lasmicon":
55-
if self.with_bandwidth:
40+
if isinstance(self.sdram_controller_settings, LASMIconSettings):
41+
if self.sdram_controller_settings.with_bandwidth:
5642
self.sdram.controller.multiplexer.add_bandwidth()
5743

58-
if self.with_memtest:
44+
if self.sdram_controller_settings.with_memtest:
5945
self.submodules.memtest_w = memtest.MemtestWriter(self.sdram.crossbar.get_master())
6046
self.submodules.memtest_r = memtest.MemtestReader(self.sdram.crossbar.get_master())
6147

62-
if self.with_l2:
48+
if self.sdram_controller_settings.with_l2:
49+
l2_size = self.sdram_controller_settings.l2_size
6350
# XXX Vivado 2014.X workaround, Vivado is not able to map correctly our L2 cache.
6451
# Issue is reported to Xilinx and should be fixed in next releases (2015.1?).
6552
# Remove this workaround when fixed by Xilinx.
6653
from mibuild.xilinx.vivado import XilinxVivadoToolchain
6754
if isinstance(self.platform.toolchain, XilinxVivadoToolchain):
6855
from migen.fhdl.simplify import FullMemoryWE
69-
self.submodules.wishbone2lasmi = FullMemoryWE(wishbone2lasmi.WB2LASMI(self.l2_size//4, self.sdram.crossbar.get_master()))
56+
self.submodules.wishbone2lasmi = FullMemoryWE(wishbone2lasmi.WB2LASMI(l2_size//4, self.sdram.crossbar.get_master()))
7057
else:
71-
self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(self.l2_size//4, self.sdram.crossbar.get_master())
58+
self.submodules.wishbone2lasmi = wishbone2lasmi.WB2LASMI(l2_size//4, self.sdram.crossbar.get_master())
7259
lasmic = self.sdram.controller.lasmic
7360
main_ram_size = 2**lasmic.aw*lasmic.dw*lasmic.nbanks//8
7461
self.register_mem("main_ram", self.mem_map["main_ram"], self.wishbone2lasmi.wishbone, main_ram_size)
7562

7663
# MINICON frontend
77-
elif self.sdram_controller_type == "minicon":
64+
elif isinstance(self.sdram_controller_settings, MiniconSettings):
7865
sdram_width = flen(self.sdram.controller.bus.dat_r)
7966
main_ram_size = 2**(geom_settings.bank_a+geom_settings.row_a+geom_settings.col_a)*sdram_width//8
8067

Diff for: ‎targets/de0nano.py

+3-1
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,7 @@
55
from misoclib.mem import sdram
66
from misoclib.mem.sdram.module import IS42S16160
77
from misoclib.mem.sdram.phy import gensdrphy
8+
from misoclib.mem.sdram.core.lasmicon import LASMIconSettings
89
from misoclib.com import uart
910
from misoclib.soc.sdram import SDRAMSoC
1011

@@ -82,10 +83,11 @@ def __init__(self, platform):
8283
class BaseSoC(SDRAMSoC):
8384
default_platform = "de0nano"
8485

85-
def __init__(self, platform, **kwargs):
86+
def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
8687
SDRAMSoC.__init__(self, platform,
8788
clk_freq=100*1000000,
8889
with_integrated_rom=True,
90+
sdram_controller_settings=sdram_controller_settings,
8991
**kwargs)
9092

9193
self.submodules.crg = _CRG(platform)

Diff for: ‎targets/kc705.py

+3-1
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,7 @@
44
from misoclib.mem import sdram
55
from misoclib.mem.sdram.module import MT8JTF12864
66
from misoclib.mem.sdram.phy import k7ddrphy
7+
from misoclib.mem.sdram.core.lasmicon import LASMIconSettings
78
from misoclib.mem.flash import spiflash
89
from misoclib.soc import mem_decoder
910
from misoclib.soc.sdram import SDRAMSoC
@@ -76,9 +77,10 @@ class BaseSoC(SDRAMSoC):
7677
}
7778
csr_map.update(SDRAMSoC.csr_map)
7879

79-
def __init__(self, platform, **kwargs):
80+
def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
8081
SDRAMSoC.__init__(self, platform,
8182
clk_freq=125*1000000, cpu_reset_address=0xaf0000,
83+
sdram_controller_settings=sdram_controller_settings,
8284
**kwargs)
8385

8486
self.submodules.crg = _CRG(platform)

Diff for: ‎targets/mlabs_video.py

+3-1
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@
88
from misoclib.mem import sdram
99
from misoclib.mem.sdram.module import MT46V32M16
1010
from misoclib.mem.sdram.phy import s6ddrphy
11+
from misoclib.mem.sdram.core.lasmicon import LASMIconSettings
1112
from misoclib.mem.flash import norflash16
1213
from misoclib.cpu.peripherals import gpio
1314
from misoclib.video import framebuffer
@@ -33,10 +34,11 @@ def __init__(self, platform):
3334
class BaseSoC(SDRAMSoC):
3435
default_platform = "mixxeo" # also supports m1
3536

36-
def __init__(self, platform, **kwargs):
37+
def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
3738
SDRAMSoC.__init__(self, platform,
3839
clk_freq=(83 + Fraction(1, 3))*1000000,
3940
cpu_reset_address=0x00180000,
41+
sdram_controller_settings=sdram_controller_settings,
4042
**kwargs)
4143

4244
self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq)

Diff for: ‎targets/pipistrello.py

+5-2
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@
66
from misoclib.mem import sdram
77
from misoclib.mem.sdram.module import MT46H32M16
88
from misoclib.mem.sdram.phy import s6ddrphy
9+
from misoclib.mem.sdram.core.lasmicon import LASMIconSettings
910
from misoclib.mem.flash import spiflash
1011
from misoclib.soc.sdram import SDRAMSoC
1112

@@ -89,12 +90,14 @@ class BaseSoC(SDRAMSoC):
8990
}
9091
csr_map.update(SDRAMSoC.csr_map)
9192

92-
def __init__(self, platform, **kwargs):
93+
def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
9394
clk_freq = 75*1000*1000
9495
if not kwargs.get("with_integrated_rom"):
9596
kwargs["rom_size"] = 0x1000000 # 128 Mb
9697
SDRAMSoC.__init__(self, platform, clk_freq,
97-
cpu_reset_address=0x170000, **kwargs) # 1.5 MB
98+
cpu_reset_address=0x170000, # 1.5 MB
99+
sdram_controller_settings=sdram_controller_settings,
100+
**kwargs)
98101

99102
self.submodules.crg = _CRG(platform, clk_freq)
100103

Diff for: ‎targets/ppro.py

+5-2
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@
66
from misoclib.mem import sdram
77
from misoclib.mem.sdram.module import MT48LC4M16
88
from misoclib.mem.sdram.phy import gensdrphy
9+
from misoclib.mem.sdram.core.lasmicon import LASMIconSettings
910
from misoclib.mem.flash import spiflash
1011
from misoclib.soc.sdram import SDRAMSoC
1112

@@ -67,10 +68,12 @@ class BaseSoC(SDRAMSoC):
6768
}
6869
csr_map.update(SDRAMSoC.csr_map)
6970

70-
def __init__(self, platform, **kwargs):
71+
def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs):
7172
clk_freq = 80*1000*1000
7273
SDRAMSoC.__init__(self, platform, clk_freq,
73-
cpu_reset_address=0x60000, **kwargs)
74+
cpu_reset_address=0x60000,
75+
sdram_controller_settings=sdram_controller_settings,
76+
**kwargs)
7477

7578
self.submodules.crg = _CRG(platform, clk_freq)
7679

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