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enjoy-digitalenjoy-digital
committedMar 21, 2015
sdram: simplify the way we pass settings to controller and rename ramcon_type to sdram_controller_type (more explicit)
·
0.120.1
1 parent 9bc71f3 commit 70469e1

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8 files changed

+29
-50
lines changed

8 files changed

+29
-50
lines changed
 

Diff for: ‎misoclib/mem/sdram/__init__.py

-2
Original file line numberDiff line numberDiff line change
@@ -9,5 +9,3 @@ def GeomSettings(bank_a, row_a, col_a):
99
return GeomSettingsT(bank_a, row_a, col_a, max(row_a, col_a))
1010

1111
TimingSettings = namedtuple("TimingSettings", "tRP tRCD tWR tWTR tREFI tRFC")
12-
13-
ControllerSettings = namedtuple("ControllerSettings", "req_queue_size read_time write_time")

Diff for: ‎misoclib/mem/sdram/core/__init__.py

+8-4
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,5 @@
1+
from collections import namedtuple
2+
13
from migen.fhdl.std import *
24
from migen.genlib.record import *
35
from migen.bank.description import *
@@ -6,24 +8,26 @@
68
from misoclib.mem.sdram.core import minicon, lasmicon
79
from misoclib.mem.sdram.core import lasmixbar
810

11+
ControllerSettings = namedtuple("ControllerSettings", "type req_queue_size read_time write_time")
12+
913
class SDRAMCore(Module, AutoCSR):
10-
def __init__(self, phy, ramcon_type, geom_settings, timing_settings, controller_settings, **kwargs):
14+
def __init__(self, phy, geom_settings, timing_settings, controller_settings, **kwargs):
1115
# DFI
1216
self.submodules.dfii = dfii.DFIInjector(geom_settings.mux_a, geom_settings.bank_a,
1317
phy.settings.dfi_d, phy.settings.nphases)
1418
self.comb += Record.connect(self.dfii.master, phy.dfi)
1519

1620
# LASMICON
17-
if ramcon_type == "lasmicon":
21+
if controller_settings.type == "lasmicon":
1822
self.submodules.controller = controller = lasmicon.LASMIcon(phy.settings, geom_settings, timing_settings,
1923
controller_settings, **kwargs)
2024
self.comb += Record.connect(controller.dfi, self.dfii.slave)
2125

2226
self.submodules.crossbar = crossbar = lasmixbar.LASMIxbar([controller.lasmic], controller.nrowbits)
2327

2428
# MINICON
25-
elif ramcon_type == "minicon":
29+
elif controller_settings.type == "minicon":
2630
self.submodules.controller = controller = minicon.Minicon(phy.settings, geom_settings, timing_settings)
2731
self.comb += Record.connect(controller.dfi, self.dfii.slave)
2832
else:
29-
raise ValueError("Unsupported SDRAM controller type: {}".format(self.ramcon_type))
33+
raise ValueError("Unsupported SDRAM controller type: {}".format(controller_settings.type))

Diff for: ‎misoclib/soc/sdram.py

+16-8
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22
from migen.bus import wishbone, csr
33
from migen.genlib.record import *
44

5-
from misoclib.mem.sdram.core import SDRAMCore
5+
from misoclib.mem.sdram.core import ControllerSettings, SDRAMCore
66
from misoclib.mem.sdram.frontend import memtest, wishbone2lasmi
77
from misoclib.soc import SoC, mem_decoder
88

@@ -16,13 +16,21 @@ class SDRAMSoC(SoC):
1616
csr_map.update(SoC.csr_map)
1717

1818
def __init__(self, platform, clk_freq,
19-
ramcon_type="lasmicon",
19+
sdram_controller_type="lasmicon", sdram_controller_req_queue_size=8,
20+
sdram_controller_read_time=32, sdram_controller_write_time=16,
2021
with_l2=True, l2_size=8192,
2122
with_bandwidth=False, # specific to LASMICON,
2223
with_memtest=False, # ignored for MINICON
2324
**kwargs):
2425
SoC.__init__(self, platform, clk_freq, **kwargs)
25-
self.ramcon_type = ramcon_type
26+
self.sdram_controller_type = sdram_controller_type
27+
self.sdram_controller_settings = ControllerSettings(
28+
type=sdram_controller_type,
29+
# Below parameters are only used by LASMIcon
30+
req_queue_size=sdram_controller_req_queue_size,
31+
read_time=sdram_controller_read_time,
32+
write_time=sdram_controller_write_time
33+
)
2634

2735
self.with_l2 = with_l2
2836
self.l2_size = l2_size
@@ -32,18 +40,18 @@ def __init__(self, platform, clk_freq,
3240

3341
self._sdram_phy_registered = False
3442

35-
def register_sdram_phy(self, phy, geom_settings, timing_settings, controller_settings):
43+
def register_sdram_phy(self, phy, geom_settings, timing_settings):
3644
if self._sdram_phy_registered:
3745
raise FinalizeError
3846
self._sdram_phy_registered = True
39-
if self.ramcon_type == "minicon" and phy.settings.memtype != "SDR":
47+
if self.sdram_controller_type == "minicon" and phy.settings.memtype != "SDR":
4048
raise NotImplementedError("Minicon only supports SDR memtype for now (" + phy.settings.memtype + ")")
4149

4250
# Core
43-
self.submodules.sdram = SDRAMCore(phy, self.ramcon_type, geom_settings, timing_settings, controller_settings)
51+
self.submodules.sdram = SDRAMCore(phy, geom_settings, timing_settings, self.sdram_controller_settings)
4452

4553
# LASMICON frontend
46-
if self.ramcon_type == "lasmicon":
54+
if self.sdram_controller_type == "lasmicon":
4755
if self.with_bandwidth:
4856
self.sdram.controller.multiplexer.add_bandwidth()
4957

@@ -66,7 +74,7 @@ def register_sdram_phy(self, phy, geom_settings, timing_settings, controller_set
6674
self.register_mem("main_ram", self.mem_map["main_ram"], self.wishbone2lasmi.wishbone, main_ram_size)
6775

6876
# MINICON frontend
69-
elif self.ramcon_type == "minicon":
77+
elif self.sdram_controller_type == "minicon":
7078
sdram_width = flen(self.sdram.controller.bus.dat_r)
7179
main_ram_size = 2**(geom_settings.bank_a+geom_settings.row_a+geom_settings.col_a)*sdram_width//8
7280

Diff for: ‎targets/de0nano.py

+1-7
Original file line numberDiff line numberDiff line change
@@ -92,13 +92,7 @@ def __init__(self, platform, **kwargs):
9292

9393
if not self.with_integrated_main_ram:
9494
sdram_module = IS42S16160(self.clk_freq)
95-
sdram_controller_settings = sdram.ControllerSettings(
96-
req_queue_size=8,
97-
read_time=32,
98-
write_time=16
99-
)
10095
self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"))
101-
self.register_sdram_phy(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings,
102-
sdram_controller_settings)
96+
self.register_sdram_phy(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings)
10397

10498
default_subtarget = BaseSoC

Diff for: ‎targets/kc705.py

+1-7
Original file line numberDiff line numberDiff line change
@@ -85,14 +85,8 @@ def __init__(self, platform, **kwargs):
8585

8686
if not self.with_integrated_main_ram:
8787
sdram_modules = MT8JTF12864(self.clk_freq)
88-
sdram_controller_settings = sdram.ControllerSettings(
89-
req_queue_size=8,
90-
read_time=32,
91-
write_time=16
92-
)
9388
self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"), memtype="DDR3")
94-
self.register_sdram_phy(self.ddrphy, sdram_modules.geom_settings, sdram_modules.timing_settings,
95-
sdram_controller_settings)
89+
self.register_sdram_phy(self.ddrphy, sdram_modules.geom_settings, sdram_modules.timing_settings)
9690

9791
spiflash_pads = platform.request("spiflash")
9892
spiflash_pads.clk = Signal()

Diff for: ‎targets/mlabs_video.py

+1-8
Original file line numberDiff line numberDiff line change
@@ -43,16 +43,9 @@ def __init__(self, platform, **kwargs):
4343

4444
if not self.with_integrated_main_ram:
4545
sdram_modules = MT46V32M16(self.clk_freq)
46-
sdram_controller_settings = sdram.ControllerSettings(
47-
req_queue_size=8,
48-
read_time=32,
49-
write_time=16
50-
)
5146
self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), memtype="DDR",
5247
rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1")
53-
self.register_sdram_phy(self.ddrphy, sdram_modules.geom_settings, sdram_modules.timing_settings,
54-
sdram_controller_settings)
55-
48+
self.register_sdram_phy(self.ddrphy, sdram_modules.geom_settings, sdram_modules.timing_settings)
5649

5750
self.comb += [
5851
self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),

Diff for: ‎targets/pipistrello.py

+1-7
Original file line numberDiff line numberDiff line change
@@ -100,11 +100,6 @@ def __init__(self, platform, **kwargs):
100100

101101
if not self.with_integrated_main_ram:
102102
sdram_module = MT46H32M16(self.clk_freq)
103-
sdram_controller_settings = sdram.ControllerSettings(
104-
req_queue_size=8,
105-
read_time=32,
106-
write_time=16
107-
)
108103
self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"),
109104
"LPDDR", rd_bitslip=1, wr_bitslip=3, dqs_ddr_alignment="C1")
110105
self.comb += [
@@ -114,8 +109,7 @@ def __init__(self, platform, **kwargs):
114109
platform.add_platform_command("""
115110
PIN "BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE;
116111
""")
117-
self.register_sdram_phy(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings,
118-
sdram_controller_settings)
112+
self.register_sdram_phy(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings)
119113

120114
self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash4x"), dummy=10, div=4)
121115
# If not in ROM, BIOS is in SPI flash

Diff for: ‎targets/ppro.py

+1-7
Original file line numberDiff line numberDiff line change
@@ -76,14 +76,8 @@ def __init__(self, platform, **kwargs):
7676

7777
if not self.with_integrated_main_ram:
7878
sdram_module = MT48LC4M16(clk_freq)
79-
sdram_controller_settings = sdram.ControllerSettings(
80-
req_queue_size=8,
81-
read_time=32,
82-
write_time=16
83-
)
8479
self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"))
85-
self.register_sdram_phy(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings,
86-
sdram_controller_settings)
80+
self.register_sdram_phy(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings)
8781

8882
self.submodules.spiflash = spiflash.SpiFlash(platform.request("spiflash2x"), dummy=4, div=6)
8983
self.flash_boot_address = 0x70000

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