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targets: fix CLKIN1_PERIOD on ppro and pipistrello
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Original file line number | Diff line number | Diff line change |
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@@ -20,7 +20,7 @@ def __init__(self, platform, clk_freq): | |
self.clk4x_wr_strb = Signal() | ||
self.clk4x_rd_strb = Signal() | ||
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f0 = 50*1000*1000 | ||
f0 = 50*10e6 | ||
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sbourdeauducq
Member
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clk50 = platform.request("clk50") | ||
clk50a = Signal() | ||
self.specials += Instance("IBUFG", i_I=clk50, o_O=clk50a) | ||
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@@ -41,7 +41,7 @@ def __init__(self, platform, clk_freq): | |
i_DADDR=0, i_DCLK=0, i_DEN=0, i_DI=0, i_DWE=0, i_RST=0, i_REL=0, | ||
p_DIVCLK_DIVIDE=1, p_CLKFBOUT_MULT=m*p//n, p_CLKFBOUT_PHASE=0., | ||
i_CLKIN1=clk50b, i_CLKIN2=0, i_CLKINSEL=1, | ||
p_CLKIN1_PERIOD=1/f0, p_CLKIN2_PERIOD=0., | ||
p_CLKIN1_PERIOD=10e9/f0, p_CLKIN2_PERIOD=0., | ||
i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, o_LOCKED=pll_lckd, | ||
o_CLKOUT0=pll[0], p_CLKOUT0_DUTY_CYCLE=.5, | ||
o_CLKOUT1=pll[1], p_CLKOUT1_DUTY_CYCLE=.5, | ||
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@@ -91,7 +91,7 @@ class BaseSoC(SDRAMSoC): | |
csr_map.update(SDRAMSoC.csr_map) | ||
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def __init__(self, platform, sdram_controller_settings=LASMIconSettings(), **kwargs): | ||
clk_freq = 75*1000*1000 | ||
clk_freq = 75*10e6 | ||
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if not kwargs.get("with_integrated_rom"): | ||
kwargs["rom_size"] = 0x1000000 # 128 Mb | ||
SDRAMSoC.__init__(self, platform, clk_freq, | ||
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Keep this integer, floating point is imprecise.