migen/genlib/io: use 0 instead of Signal() for default rst value (imm…

…utable thanks sb)
m-labs · Mar 18, 2015 · 2fc2f8a · 2fc2f8a
1 parent bdc47b2
commit 2fc2f8a
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/migen/genlib/io.py b/migen/genlib/io.py
@@ -35,7 +35,7 @@ def lower(dr):
 		raise NotImplementedError("Attempted to use a differential output, but platform does not support them")
 
 class CRG(Module):
-	def __init__(self, clk, rst=Signal()):
+	def __init__(self, clk, rst=0):
 		self.clock_domains.cd_sys = ClockDomain()
 		self.clock_domains.cd_por = ClockDomain(reset_less=True)