Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: m-labs/migen
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: e07b7f632cef
Choose a base ref
...
head repository: m-labs/migen
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: 89fefef3f8fc
Choose a head ref
  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Mar 17, 2015

  1. Copy the full SHA
    500e58c View commit details
  2. 2
    Copy the full SHA
    89fefef View commit details
Showing with 5 additions and 2 deletions.
  1. +3 −0 mibuild/platforms/versa.py
  2. +2 −2 migen/genlib/io.py
3 changes: 3 additions & 0 deletions mibuild/platforms/versa.py
Original file line number Diff line number Diff line change
@@ -79,6 +79,9 @@ class Platform(LatticePlatform):

def __init__(self):
LatticePlatform.__init__(self, "LFE3-35EA-6FN484C", _io)

def do_finalize(self, fragment):
LatticePlatform.do_finalize(self, fragment)
try:
self.add_period_constraint(self.lookup_request("eth_clocks", 0).rx, 8.0)
except ConstraintError:
4 changes: 2 additions & 2 deletions migen/genlib/io.py
Original file line number Diff line number Diff line change
@@ -35,7 +35,7 @@ def lower(dr):
raise NotImplementedError("Attempted to use a differential output, but platform does not support them")

class CRG(Module):
def __init__(self, clk):
def __init__(self, clk, rst=Signal()):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)

@@ -46,7 +46,7 @@ def __init__(self, clk):

# Power on Reset (vendor agnostic)
rst_n = Signal()
self.sync.por += rst_n.eq(1)
self.sync.por += rst_n.eq(1 & ~rst)
self.comb += [
self.cd_sys.clk.eq(clk),
self.cd_por.clk.eq(clk),