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base repository: m-labs/misoc
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head repository: m-labs/misoc
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compare: cb4be529226d
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  • 4 commits
  • 9 files changed
  • 1 contributor

Commits on Mar 17, 2015

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3 changes: 2 additions & 1 deletion misoclib/com/liteeth/example_designs/test/make.py
Original file line number Diff line number Diff line change
@@ -18,7 +18,8 @@ def _get_args():
args = _get_args()
if args.bridge == "uart":
from misoclib.tools.litescope.host.driver.uart import LiteScopeUARTDriver
wb = LiteScopeUARTDriver(args.port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
port = args.port if not args.port.isdigit() else int(args.port)
wb = LiteScopeUARTDriver(port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
elif args.bridge == "etherbone":
from misoclib.tools.litescope.host.driver.etherbone import LiteScopeEtherboneDriver
wb = LiteScopeEtherboneDriver(args.ip_address, int(args.udp_port), "./csr.csv", int(args.busword), debug=False)
2 changes: 1 addition & 1 deletion misoclib/com/liteeth/example_designs/test/test_regs.py
Original file line number Diff line number Diff line change
@@ -4,7 +4,7 @@ def main(wb):
###
print("sysid : 0x{:04x}".format(regs.identifier_sysid.read()))
print("revision : 0x{:04x}".format(regs.identifier_revision.read()))
print("frequency : 0x{:04x}MHz".format(int(regs.identifier_frequency.read()/1000000)))
print("frequency : {}MHz".format(int(regs.identifier_frequency.read()/1000000)))
SRAM_BASE = 0x02000000
wb.write(SRAM_BASE, [i for i in range(64)])
print(wb.read(SRAM_BASE, 64))
3 changes: 2 additions & 1 deletion misoclib/mem/litesata/example_designs/test/make.py
Original file line number Diff line number Diff line change
@@ -18,7 +18,8 @@ def _get_args():
args = _get_args()
if args.bridge == "uart":
from misoclib.tools.litescope.host.driver.uart import LiteScopeUARTDriver
wb = LiteScopeUARTDriver(args.port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
port = args.port if not args.port.isdigit() else int(args.port)
wb = LiteScopeUARTDriver(port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
elif args.bridge == "etherbone":
from misoclib.tools.litescope.host.driver.etherbone import LiteScopeEtherboneDriver
wb = LiteScopeEtherboneDriver(args.ip_address, int(args.udp_port), "./csr.csv", int(args.busword), debug=False)
2 changes: 1 addition & 1 deletion misoclib/mem/litesata/example_designs/test/test_regs.py
Original file line number Diff line number Diff line change
@@ -4,6 +4,6 @@ def main(wb):
###
print("sysid : 0x{:04x}".format(regs.identifier_sysid.read()))
print("revision : 0x{:04x}".format(regs.identifier_revision.read()))
print("frequency : 0x{:04x}MHz".format(int(regs.identifier_frequency.read()/1000000)))
print("frequency : {}MHz".format(int(regs.identifier_frequency.read()/1000000)))
###
wb.close()
3 changes: 2 additions & 1 deletion misoclib/tools/litescope/example_designs/test/make.py
Original file line number Diff line number Diff line change
@@ -18,7 +18,8 @@ def _get_args():
args = _get_args()
if args.bridge == "uart":
from misoclib.tools.litescope.host.driver.uart import LiteScopeUARTDriver
wb = LiteScopeUARTDriver(args.port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
port = args.port if not args.port.isdigit() else int(args.port)
wb = LiteScopeUARTDriver(port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
elif args.bridge == "etherbone":
from misoclib.tools.litescope.host.driver.etherbone import LiteScopeEtherboneDriver
wb = LiteScopeEtherboneDriver(args.ip_address, int(args.udp_port), "./csr.csv", int(args.busword), debug=False)
2 changes: 1 addition & 1 deletion misoclib/tools/litescope/example_designs/test/test_regs.py
Original file line number Diff line number Diff line change
@@ -4,6 +4,6 @@ def main(wb):
###
print("sysid : 0x{:04x}".format(regs.identifier_sysid.read()))
print("revision : 0x{:04x}".format(regs.identifier_revision.read()))
print("frequency : 0x{:04x}MHz".format(int(regs.identifier_frequency.read()/1000000)))
print("frequency : {}MHz".format(int(regs.identifier_frequency.read()/1000000)))
###
wb.close()
3 changes: 2 additions & 1 deletion misoclib/tools/litescope/host/driver/etherbone.py
Original file line number Diff line number Diff line change
@@ -11,7 +11,8 @@ def __init__(self, ip_address, udp_port=20000, addrmap=None, busword=8, debug=Fa

self.tx_sock = None
self.rx_sock = None
self.regs = build_map(addrmap, busword, self.read, self.write)
if addrmap is not None:
self.regs = build_map(addrmap, busword, self.read, self.write)

def open(self):
self.tx_sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
3 changes: 2 additions & 1 deletion misoclib/tools/litescope/host/driver/uart.py
Original file line number Diff line number Diff line change
@@ -15,7 +15,8 @@ def __init__(self, port, baudrate=115200, addrmap=None, busword=8, debug=False):
self.baudrate = str(baudrate)
self.debug = debug
self.uart = serial.Serial(port, baudrate, timeout=0.25)
self.regs = build_map(addrmap, busword, self.read, self.write)
if addrmap is not None:
self.regs = build_map(addrmap, busword, self.read, self.write)

def open(self):
self.uart.flushOutput()
17 changes: 17 additions & 0 deletions targets/versa.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,17 @@
from migen.fhdl.std import *
from migen.bus import wishbone
from migen.genlib.io import CRG

from misoclib.soc import SoC

class BaseSoC(SoC):
default_platform = "versa"
def __init__(self, platform, **kwargs):
SoC.__init__(self, platform,
clk_freq=100*1000000,
with_rom=True,
**kwargs)
self.submodules.crg = CRG(platform.request("clk100"), ~platform.request("rst_n"))
self.comb += platform.request("user_led", 0).eq(ResetSignal())

default_subtarget = BaseSoC