m-labs · Mar 21, 2015 · Mar 21, 2015 · Mar 21, 2015 · Mar 21, 2015 · Mar 21, 2015
diff --git a/misoclib/mem/sdram/__init__.py b/misoclib/mem/sdram/__init__.py
@@ -8,5 +8,6 @@ def PhySettings(memtype, dfi_d, nphases, rdphase, wrphase, rdcmdphase, wrcmdphas
 def GeomSettings(bank_a, row_a, col_a):
 	return GeomSettingsT(bank_a, row_a, col_a, max(row_a, col_a))
 
-TimingSettings = namedtuple("TimingSettings", "tRP tRCD tWR tWTR tREFI tRFC" \
-	" req_queue_size read_time write_time")
+TimingSettings = namedtuple("TimingSettings", "tRP tRCD tWR tWTR tREFI tRFC")
+
+ControllerSettings = namedtuple("ControllerSettings", "req_queue_size read_time write_time")
diff --git a/misoclib/mem/sdram/core/__init__.py b/misoclib/mem/sdram/core/__init__.py
@@ -7,22 +7,23 @@
 from misoclib.mem.sdram.core import lasmixbar
 
 class SDRAMCore(Module, AutoCSR):
-	def __init__(self, phy, ramcon_type, sdram_geom, sdram_timing, **kwargs):
+	def __init__(self, phy, ramcon_type, geom_settings, timing_settings, controller_settings, **kwargs):
 		# DFI
-		self.submodules.dfii = dfii.DFIInjector(sdram_geom.mux_a, sdram_geom.bank_a,
+		self.submodules.dfii = dfii.DFIInjector(geom_settings.mux_a, geom_settings.bank_a,
 				phy.settings.dfi_d, phy.settings.nphases)
 		self.comb += Record.connect(self.dfii.master, phy.dfi)
 
 		# LASMICON
 		if ramcon_type == "lasmicon":
-			self.submodules.controller = controller = lasmicon.LASMIcon(phy.settings, sdram_geom, sdram_timing, **kwargs)
+			self.submodules.controller = controller = lasmicon.LASMIcon(phy.settings, geom_settings, timing_settings,
+				controller_settings, **kwargs)
 			self.comb += Record.connect(controller.dfi, self.dfii.slave)
 
 			self.submodules.crossbar = crossbar = lasmixbar.LASMIxbar([controller.lasmic], controller.nrowbits)
 
 		# MINICON
 		elif ramcon_type == "minicon":
-			self.submodules.controller = controller = minicon.Minicon(phy.settings, sdram_geom, sdram_timing)
+			self.submodules.controller = controller = minicon.Minicon(phy.settings, geom_settings, timing_settings)
 			self.comb += Record.connect(controller.dfi, self.dfii.slave)
 		else:
 			raise ValueError("Unsupported SDRAM controller type: {}".format(self.ramcon_type))
diff --git a/misoclib/mem/sdram/core/lasmicon/__init__.py b/misoclib/mem/sdram/core/lasmicon/__init__.py
@@ -7,7 +7,7 @@
 from misoclib.mem.sdram.core.lasmicon.multiplexer import *
 
 class LASMIcon(Module):
-	def __init__(self, phy_settings, geom_settings, timing_settings, **kwargs):
+	def __init__(self, phy_settings, geom_settings, timing_settings, controller_settings, **kwargs):
 		if phy_settings.memtype in ["SDR"]:
 			burst_length = phy_settings.nphases*1 # command multiplication*SDR
 		elif phy_settings.memtype in ["DDR", "LPDDR", "DDR2", "DDR3"]:
@@ -22,7 +22,7 @@ def __init__(self, phy_settings, geom_settings, timing_settings, **kwargs):
 			aw=geom_settings.row_a + geom_settings.col_a - address_align,
 			dw=phy_settings.dfi_d*phy_settings.nphases,
 			nbanks=2**geom_settings.bank_a,
-			req_queue_size=timing_settings.req_queue_size,
+			req_queue_size=controller_settings.req_queue_size,
 			read_latency=phy_settings.read_latency+1,
 			write_latency=phy_settings.write_latency+1)
 		self.nrowbits = geom_settings.col_a - address_align
@@ -31,10 +31,10 @@ def __init__(self, phy_settings, geom_settings, timing_settings, **kwargs):
 
 		self.submodules.refresher = Refresher(geom_settings.mux_a, geom_settings.bank_a,
 			timing_settings.tRP, timing_settings.tREFI, timing_settings.tRFC)
-		self.submodules.bank_machines = [BankMachine(geom_settings, timing_settings, address_align, i,
+		self.submodules.bank_machines = [BankMachine(geom_settings, timing_settings, controller_settings, address_align, i,
 				getattr(self.lasmic, "bank"+str(i)))
 			for i in range(2**geom_settings.bank_a)]
-		self.submodules.multiplexer = Multiplexer(phy_settings, geom_settings, timing_settings,
+		self.submodules.multiplexer = Multiplexer(phy_settings, geom_settings, timing_settings, controller_settings,
 			self.bank_machines, self.refresher,
 			self.dfi, self.lasmic,
 			**kwargs)

diff --git a/misoclib/mem/sdram/core/lasmicon/bankmachine.py b/misoclib/mem/sdram/core/lasmicon/bankmachine.py
@@ -26,15 +26,15 @@ def col(self, address):
 			return Cat(Replicate(0, self.address_align), address[:split])
 
 class BankMachine(Module):
-	def __init__(self, geom_settings, timing_settings, address_align, bankn, req):
+	def __init__(self, geom_settings, timing_settings, controller_settings, address_align, bankn, req):
 		self.refresh_req = Signal()
 		self.refresh_gnt = Signal()
 		self.cmd = CommandRequestRW(geom_settings.mux_a, geom_settings.bank_a)
 
 		###
 
 		# Request FIFO
-		self.submodules.req_fifo = SyncFIFO([("we", 1), ("adr", flen(req.adr))], timing_settings.req_queue_size)
+		self.submodules.req_fifo = SyncFIFO([("we", 1), ("adr", flen(req.adr))], controller_settings.req_queue_size)
 		self.comb += [
 			self.req_fifo.din.we.eq(req.we),
 			self.req_fifo.din.adr.eq(req.adr),

diff --git a/misoclib/mem/sdram/core/lasmicon/multiplexer.py b/misoclib/mem/sdram/core/lasmicon/multiplexer.py
@@ -89,7 +89,7 @@ def stb_and(cmd, attr):
 			]
 
 class Multiplexer(Module, AutoCSR):
-	def __init__(self, phy_settings, geom_settings, timing_settings, bank_machines, refresher, dfi, lasmic,
+	def __init__(self, phy_settings, geom_settings, timing_settings, controller_settings, bank_machines, refresher, dfi, lasmic,
 			with_bandwidth=False):
 		assert(phy_settings.nphases == len(dfi.phases))
 
@@ -137,8 +137,8 @@ def anti_starvation(timeout):
 			else:
 				self.comb += max_time.eq(0)
 			return en, max_time
-		read_time_en, max_read_time = anti_starvation(timing_settings.read_time)
-		write_time_en, max_write_time = anti_starvation(timing_settings.write_time)
+		read_time_en, max_read_time = anti_starvation(controller_settings.read_time)
+		write_time_en, max_write_time = anti_starvation(controller_settings.write_time)
 
 		# Refresh
 		self.comb += [bm.refresh_req.eq(refresher.req) for bm in bank_machines]

diff --git a/misoclib/mem/sdram/module.py b/misoclib/mem/sdram/module.py
@@ -0,0 +1,139 @@
+# SDRAM memory modules library
+#
+# This library avoid duplications of memory modules definitions in targets and
+# ease SDRAM usage. (User can only select an already existing module or create
+# one for its board and contribute to this library)
+#
+# TODO:
+#   Try to share the maximum information we can between modules:
+#    - ex: MT46V32M16 and MT46H32M16 are almost identical (V=DDR, H=LPDDR)
+#    - Modules can have different configuration:
+#        MT8JTF12864 (1GB), MT8JTF25664 (2GB)
+#      but share all others informations, try to create an unique module for all
+#      configurations.
+#    - Modules can have different speedgrades, add support for it (and also add
+#      a check to verify clk_freq is in the supported range)
+
+from math import ceil
+
+from migen.fhdl.std import *
+from misoclib.mem import sdram
+
+class SDRAMModule:
+	def __init__(self, clk_freq, geom_settings, timing_settings):
+		self.clk_freq = clk_freq
+		self.geom_settings = sdram.GeomSettings(
+			bank_a=log2_int(geom_settings["nbanks"]),
+			row_a=log2_int(geom_settings["nrows"]),
+			col_a=log2_int(geom_settings["ncols"])
+		)
+		self.timing_settings = sdram.TimingSettings(
+			tRP=self.ns(timing_settings["tRP"]),
+			tRCD=self.ns(timing_settings["tRCD"]),
+			tWR=self.ns(timing_settings["tWR"]),
+			tWTR=timing_settings["tWTR"],
+			tREFI=self.ns(timing_settings["tREFI"], False),
+			tRFC=self.ns(timing_settings["tRFC"])
+		)
+
+	def ns(self, t, margin=True):
+		clk_period_ns = 1000000000/self.clk_freq
+		if margin:
+			t += clk_period_ns/2
+		return ceil(t/clk_period_ns)
+
+# SDR
+class IS42S16160(SDRAMModule):
+	geom_settings = {
+		"nbanks": 	4,
+		"nrows":	8192,
+		"ncols":	512
+	}
+	timing_settings = {
+		"tRP":		20,
+		"tRCD":		20,
+		"tWR":		20,
+		"tWTR":		2,
+		"tREFI":	7800,
+		"tRFC":		70
+	}
+	def __init__(self, clk_freq):
+		SDRAMModule.__init__(self, clk_freq, self.geom_settings,
+			self.timing_settings)
+
+class MT48LC4M16(SDRAMModule):
+	geom_settings = {
+		"nbanks":	4,
+		"nrows":	4096,
+		"ncols":	256
+	}
+	timing_settings = {
+		"tRP":		15,
+		"tRCD":		15,
+		"tWR":		14,
+		"tWTR":		2,
+		"tREFI":	64*1000*1000/4096,
+		"tRFC":		66
+	}
+	def __init__(self, clk_freq):
+		SDRAMModule.__init__(self, clk_freq, self.geom_settings,
+			self.timing_settings)
+
+# DDR
+class MT46V32M16(SDRAMModule):
+	geom_settings = {
+		"nbanks":	4,
+		"nrows":	8192,
+		"ncols":	1024
+	}
+	timing_settings = {
+		"tRP":		15,
+		"tRCD":		15,
+		"tWR":		15,
+		"tWTR":		2,
+		"tREFI":	7800,
+		"tRFC":		70
+	}
+	def __init__(self, clk_freq):
+		SDRAMModule.__init__(self, clk_freq, self.geom_settings,
+			self.timing_settings)
+
+# LPDDR
+class MT46H32M16(SDRAMModule):
+	geom_settings = {
+		"nbanks":	4,
+		"nrows":	8192,
+		"ncols":	1024
+	}
+	timing_settings = {
+		"tRP":		15,
+		"tRCD":		15,
+		"tWR":		15,
+		"tWTR":		2,
+		"tREFI":	64*1000*1000/8192,
+		"tRFC":		72
+	}
+	def __init__(self, clk_freq):
+		SDRAMModule.__init__(self, clk_freq, self.geom_settings,
+			self.timing_settings)
+
+# DDR2
+
+# DDR3
+class MT8JTF12864(SDRAMModule):
+	geom_settings = {
+		"nbanks":	8,
+		"nrows":	65536,
+		"ncols":	1024
+	}
+	timing_settings = {
+		"tRP":		15,
+		"tRCD":		15,
+		"tWR":		15,
+		"tWTR":		2,
+		"tREFI":	7800,
+		"tRFC":		70
+	}
+	def __init__(self, clk_freq):
+		SDRAMModule.__init__(self, clk_freq, self.geom_settings,
+			self.timing_settings)
diff --git a/misoclib/soc/sdram.py b/misoclib/soc/sdram.py
@@ -32,15 +32,15 @@ def __init__(self, platform, clk_freq,
 
 		self._sdram_phy_registered = False
 
-	def register_sdram_phy(self, phy, sdram_geom, sdram_timing):
+	def register_sdram_phy(self, phy, geom_settings, timing_settings, controller_settings):
 		if self._sdram_phy_registered:
 			raise FinalizeError
 		self._sdram_phy_registered = True
 		if self.ramcon_type == "minicon" and phy.settings.memtype != "SDR":
 			raise NotImplementedError("Minicon only supports SDR memtype for now (" + phy.settings.memtype + ")")
 
 		# Core
-		self.submodules.sdram = SDRAMCore(phy, self.ramcon_type, sdram_geom, sdram_timing)
+		self.submodules.sdram = SDRAMCore(phy, self.ramcon_type, geom_settings, timing_settings, controller_settings)
 
 		# LASMICON frontend
 		if self.ramcon_type == "lasmicon":
@@ -68,7 +68,7 @@ def register_sdram_phy(self, phy, sdram_geom, sdram_timing):
 		# MINICON frontend
 		elif self.ramcon_type == "minicon":
 			sdram_width = flen(self.sdram.controller.bus.dat_r)
-			main_ram_size = 2**(sdram_geom.bank_a+sdram_geom.row_a+sdram_geom.col_a)*sdram_width//8
+			main_ram_size = 2**(geom_settings.bank_a+geom_settings.row_a+geom_settings.col_a)*sdram_width//8
 
 			if sdram_width == 32:
 				self.register_mem("sdram", self.mem_map["sdram"], self.sdram.controller.bus, main_ram_size)

diff --git a/targets/de0nano.py b/targets/de0nano.py
@@ -3,6 +3,7 @@
 
 from misoclib.cpu.peripherals import gpio
 from misoclib.mem import sdram
+from misoclib.mem.sdram.module import IS42S16160
 from misoclib.mem.sdram.phy import gensdrphy
 from misoclib.com import uart
 from misoclib.soc.sdram import SDRAMSoC
@@ -90,26 +91,14 @@ def __init__(self, platform, **kwargs):
 		self.submodules.crg = _CRG(platform)
 
 		if not self.with_main_ram:
-			sdram_geom = sdram.GeomSettings(
-				bank_a=2,
-				row_a=13,
-				col_a=9
-			)
-
-			sdram_timing = sdram.TimingSettings(
-				tRP=self.ns(20),
-				tRCD=self.ns(20),
-				tWR=self.ns(20),
-				tWTR=2,
-				tREFI=self.ns(7800, False),
-				tRFC=self.ns(70),
-
+			sdram_module = IS42S16160(self.clk_freq)
+			sdram_controller_settings = sdram.ControllerSettings(
 				req_queue_size=8,
 				read_time=32,
 				write_time=16
 			)
-
 			self.submodules.sdrphy = gensdrphy.GENSDRPHY(platform.request("sdram"))
-			self.register_sdram_phy(self.sdrphy, sdram_geom, sdram_timing)
+			self.register_sdram_phy(self.sdrphy, sdram_module.geom_settings, sdram_module.timing_settings,
+				sdram_controller_settings)
 
 default_subtarget = BaseSoC
diff --git a/targets/kc705.py b/targets/kc705.py
@@ -2,6 +2,7 @@
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from misoclib.mem import sdram
+from misoclib.mem.sdram.module import MT8JTF12864
 from misoclib.mem.sdram.phy import k7ddrphy
 from misoclib.mem.flash import spiflash
 from misoclib.soc import mem_decoder
@@ -83,25 +84,15 @@ def __init__(self, platform, **kwargs):
 		self.submodules.crg = _CRG(platform)
 
 		if not self.with_main_ram:
-			sdram_geom = sdram.GeomSettings(
-				bank_a=3,
-				row_a=16,
-				col_a=10
-			)
-			sdram_timing = sdram.TimingSettings(
-				tRP=self.ns(15),
-				tRCD=self.ns(15),
-				tWR=self.ns(15),
-				tWTR=2,
-				tREFI=self.ns(7800, False),
-				tRFC=self.ns(70),
-
+			sdram_module = MT8JTF12864(self.clk_freq)
+			sdram_controller_settings = sdram.ControllerSettings(
 				req_queue_size=8,
 				read_time=32,
 				write_time=16
 			)
 			self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"), memtype="DDR3")
-			self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing)
+			self.register_sdram_phy(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings,
+				sdram_controller_settings)
 
 		spiflash_pads = platform.request("spiflash")
 		spiflash_pads.clk = Signal()

diff --git a/targets/mlabs_video.py b/targets/mlabs_video.py
@@ -6,6 +6,7 @@
 
 from misoclib.others import mxcrg
 from misoclib.mem import sdram
+from misoclib.mem.sdram.module import MT46V32M16
 from misoclib.mem.sdram.phy import s6ddrphy
 from misoclib.mem.flash import norflash16
 from misoclib.cpu.peripherals import gpio
@@ -41,26 +42,16 @@ def __init__(self, platform, **kwargs):
 		self.submodules.crg = mxcrg.MXCRG(_MXClockPads(platform), self.clk_freq)
 
 		if not self.with_main_ram:
-			sdram_geom = sdram.GeomSettings(
-				bank_a=2,
-				row_a=13,
-				col_a=10
-			)
-			sdram_timing = sdram.TimingSettings(
-				tRP=self.ns(15),
-				tRCD=self.ns(15),
-				tWR=self.ns(15),
-				tWTR=2,
-				tREFI=self.ns(7800, False),
-				tRFC=self.ns(70),
-
+			sdram_module = MT46V32M16(self.clk_freq)
+			sdram_controller_settings =  sdram.ControllerSettings(
 				req_queue_size=8,
 				read_time=32,
 				write_time=16
 			)
 			self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"), memtype="DDR",
 				rd_bitslip=0, wr_bitslip=3, dqs_ddr_alignment="C1")
-			self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing)
+			self.register_sdram_phy(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings,
+				sdram_controller_settings)
 
 
 			self.comb += [