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Sebastien Bourdeauducq
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Jun 17, 2012
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Original file line number | Diff line number | Diff line change |
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from migen.fhdl.structure import * | ||
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class Framebuffer: | ||
def __init__(self, csr_address, asmiport): | ||
# VGA clock input | ||
self.vga_clk = Signal() | ||
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# pads | ||
self.vga_psave_n = Signal() | ||
self.vga_hsync_n = Signal() | ||
self.vga_vsync_n = Signal() | ||
self.vga_sync_n = Signal() | ||
self.vga_blank_n = Signal() | ||
self.vga_r = Signal(BV(8)) | ||
self.vga_g = Signal(BV(8)) | ||
self.vga_b = Signal(BV(8)) | ||
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def get_fragment(self): | ||
return Fragment() |
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