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  • 5 commits
  • 15 files changed
  • 1 contributor

Commits on Mar 12, 2013

  1. fhdl/verilog: implicit get_fragment

    Sebastien Bourdeauducq committed Mar 12, 2013
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    ecfe164 View commit details
  2. examples/basic: use new APIs

    Sebastien Bourdeauducq committed Mar 12, 2013
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    907bfa8 View commit details
  3. vpi: make it work by default on Arch

    Sebastien Bourdeauducq committed Mar 12, 2013
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    d92ca43 View commit details
  4. sim/generic: support implicit get_fragment

    Sebastien Bourdeauducq committed Mar 12, 2013
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    69dbf84 View commit details
  5. examples/pytholite: use new APIs

    Sebastien Bourdeauducq committed Mar 12, 2013
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    c99cc93 View commit details
34 changes: 16 additions & 18 deletions examples/basic/arrays.py
Original file line number Diff line number Diff line change
@@ -1,25 +1,23 @@
from migen.fhdl.structure import *
from migen.fhdl.module import Module
from migen.fhdl import verilog

dx = 5
dy = 5
class Example(Module):
def __init__(self):
dx = 5
dy = 5

x = Signal(max=dx)
y = Signal(max=dy)
out = Signal()
x = Signal(max=dx)
y = Signal(max=dy)
out = Signal()

my_2d_array = Array(Array(Signal() for a in range(dx)) for b in range(dy))
comb = [
out.eq(my_2d_array[x][y])
]
my_2d_array = Array(Array(Signal() for a in range(dx)) for b in range(dy))
self.comb += out.eq(my_2d_array[x][y])

we = Signal()
inp = Signal()
sync = [
If(we,
my_2d_array[x][y].eq(inp)
)
]
we = Signal()
inp = Signal()
self.sync += If(we,
my_2d_array[x][y].eq(inp)
)

f = Fragment(comb, sync)
print(verilog.convert(f))
print(verilog.convert(Example()))
27 changes: 15 additions & 12 deletions examples/basic/complex.py
Original file line number Diff line number Diff line change
@@ -1,16 +1,19 @@
from migen.fhdl.module import Module
from migen.genlib.complex import *
from migen.fhdl import verilog

w = Complex(32, 42)
A = SignalC(16)
B = SignalC(16)
Bw = SignalC(16, variable=True)
C = SignalC(16)
D = SignalC(16)
sync = [
Bw.eq(B*w),
C.eq(A + Bw),
D.eq(A - Bw)
]
class Example(Module):
def __init__(self):
w = Complex(32, 42)
A = SignalC(16)
B = SignalC(16)
Bw = SignalC(16, variable=True)
C = SignalC(16)
D = SignalC(16)
self.sync += [
Bw.eq(B*w),
C.eq(A + Bw),
D.eq(A - Bw)
]

print(verilog.convert(Fragment(sync=sync)))
print(verilog.convert(Example()))
16 changes: 11 additions & 5 deletions examples/basic/fsm.py
Original file line number Diff line number Diff line change
@@ -1,9 +1,15 @@
from migen.fhdl.structure import *
from migen.fhdl.module import Module
from migen.fhdl import verilog
from migen.genlib.fsm import FSM

s = Signal()
myfsm = FSM("FOO", "BAR")
myfsm.act(myfsm.FOO, s.eq(1), myfsm.next_state(myfsm.BAR))
myfsm.act(myfsm.BAR, s.eq(0), myfsm.next_state(myfsm.FOO))
print(verilog.convert(myfsm.get_fragment(), {s}))
class Example(Module):
def __init__(self):
self.s = Signal()
myfsm = FSM("FOO", "BAR")
self.submodules += myfsm
myfsm.act(myfsm.FOO, self.s.eq(1), myfsm.next_state(myfsm.BAR))
myfsm.act(myfsm.BAR, self.s.eq(0), myfsm.next_state(myfsm.FOO))

example = Example()
print(verilog.convert(example, {example.s}))
60 changes: 0 additions & 60 deletions examples/basic/lm32_inst.py

This file was deleted.

17 changes: 10 additions & 7 deletions examples/basic/memory.py
Original file line number Diff line number Diff line change
@@ -1,12 +1,15 @@
from migen.fhdl.structure import Fragment
from migen.fhdl.specials import Memory
from migen.fhdl.module import Module
from migen.fhdl import verilog

mem = Memory(32, 100, init=[5, 18, 32])
p1 = mem.get_port(write_capable=True, we_granularity=8)
p2 = mem.get_port(has_re=True, clock_domain="rd")
class Example(Module):
def __init__(self):
self.specials.mem = Memory(32, 100, init=[5, 18, 32])
p1 = self.mem.get_port(write_capable=True, we_granularity=8)
p2 = self.mem.get_port(has_re=True, clock_domain="rd")
self.ios = {p1.adr, p1.dat_r, p1.we, p1.dat_w,
p2.adr, p2.dat_r, p2.re}

f = Fragment(specials={mem})
v = verilog.convert(f, ios={p1.adr, p1.dat_r, p1.we, p1.dat_w,
p2.adr, p2.dat_r, p2.re})
print(v)
example = Example()
print(verilog.convert(example, example.ios))
26 changes: 14 additions & 12 deletions examples/basic/namer.py
Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
from migen.fhdl.structure import *
from migen.fhdl import verilog
from migen.fhdl.module import Module
from migen.genlib.misc import optree

def gen_list(n):
@@ -24,17 +25,18 @@ class Toto:
def __init__(self):
self.sigs = gen_list(2)

a = [Bar() for x in range(3)]
b = [Foo() for x in range(3)]
c = b
b = [Bar() for x in range(2)]
class Example(Module):
def __init__(self):
a = [Bar() for x in range(3)]
b = [Foo() for x in range(3)]
c = b
b = [Bar() for x in range(2)]

output = Signal()
allsigs = []
for lst in [a, b, c]:
for obj in lst:
allsigs.extend(obj.sigs)
comb = [output.eq(optree("|", allsigs))]
output = Signal()
allsigs = []
for lst in [a, b, c]:
for obj in lst:
allsigs.extend(obj.sigs)
self.comb += output.eq(optree("|", allsigs))

f = Fragment(comb)
print(verilog.convert(f))
print(verilog.convert(Example()))
3 changes: 1 addition & 2 deletions examples/basic/psync.py
Original file line number Diff line number Diff line change
@@ -15,6 +15,5 @@ def lower(dr):
return XilinxMultiRegImpl(dr.i, dr.idomain, dr.o, dr.odomain, dr.n)

ps = PulseSynchronizer("from", "to")
f = ps.get_fragment()
v = verilog.convert(f, {ps.i, ps.o}, special_overrides={MultiReg: XilinxMultiReg})
v = verilog.convert(ps, {ps.i, ps.o}, special_overrides={MultiReg: XilinxMultiReg})
print(v)
35 changes: 21 additions & 14 deletions examples/basic/simple_gpio.py
Original file line number Diff line number Diff line change
@@ -1,23 +1,30 @@
from migen.fhdl.structure import *
from migen.fhdl.module import Module
from migen.fhdl import verilog
from migen.genlib.cdc import MultiReg
from migen.bank import description, csrgen
from migen.bank.description import READ_ONLY, WRITE_ONLY

ninputs = 32
noutputs = 32
class Example(Module):
def __init__(self, ninputs=32, noutputs=32):
r_o = description.RegisterField(noutputs, atomic_write=True)
r_i = description.RegisterField(ninputs, READ_ONLY, WRITE_ONLY)

oreg = description.RegisterField("o", noutputs, atomic_write=True)
ireg = description.RegisterField("i", ninputs, READ_ONLY, WRITE_ONLY)
self.submodules.bank = csrgen.Bank([r_o, r_i])
self.gpio_in = Signal(ninputs)
self.gpio_out = Signal(ninputs)

# input path
gpio_in = Signal(ninputs)
gpio_in_s = Signal(ninputs) # synchronizer
insync = [gpio_in_s.eq(gpio_in), ireg.field.w.eq(gpio_in_s)]
inf = Fragment(sync=insync)
###

bank = csrgen.Bank([oreg, ireg])
f = bank.get_fragment() + inf
oreg.field.r.name_override = "gpio_out"
i = bank.interface
v = verilog.convert(f, {i.dat_r, oreg.field.r, i.adr, i.we, i.dat_w, gpio_in})
gpio_in_s = Signal(ninputs)
self.specials += MultiReg(self.gpio_in, "ext", gpio_in_s, "sys")
self.comb += [
r_i.field.w.eq(gpio_in_s),
self.gpio_out.eq(r_o.field.r)
]

example = Example()
i = example.bank.bus
v = verilog.convert(example, {i.dat_r, i.adr, i.we, i.dat_w,
example.gpio_in, example.gpio_out})
print(v)
18 changes: 11 additions & 7 deletions examples/basic/tristate.py
Original file line number Diff line number Diff line change
@@ -1,12 +1,16 @@
from migen.fhdl.structure import *
from migen.fhdl.specials import Tristate
from migen.fhdl.module import Module
from migen.fhdl import verilog

n = 6
pad = Signal(n)
o = Signal(n)
oe = Signal()
i = Signal(n)
class Example(Module):
def __init__(self, n=6):
self.pad = Signal(n)
self.o = Signal(n)
self.oe = Signal()
self.i = Signal(n)

f = Fragment(specials={Tristate(pad, o, oe, i)})
print(verilog.convert(f, ios={pad, o, oe, i}))
self.specials += Tristate(self.pad, self.o, self.oe, self.i)

e = Example()
print(verilog.convert(e, ios={e.pad, e.o, e.oe, e.i}))
19 changes: 12 additions & 7 deletions examples/basic/two_dividers.py
Original file line number Diff line number Diff line change
@@ -1,10 +1,15 @@
from migen.fhdl import verilog
from migen.fhdl.module import Module
from migen.genlib import divider

d1 = divider.Divider(16)
d2 = divider.Divider(16)
frag = d1.get_fragment() + d2.get_fragment()
o = verilog.convert(frag, {
d1.ready_o, d1.quotient_o, d1.remainder_o, d1.start_i, d1.dividend_i, d1.divisor_i,
d2.ready_o, d2.quotient_o, d2.remainder_o, d2.start_i, d2.dividend_i, d2.divisor_i})
print(o)
class Example(Module):
def __init__(self):
d1 = divider.Divider(16)
d2 = divider.Divider(16)
self.submodules += d1, d2
self.ios = {
d1.ready_o, d1.quotient_o, d1.remainder_o, d1.start_i, d1.dividend_i, d1.divisor_i,
d2.ready_o, d2.quotient_o, d2.remainder_o, d2.start_i, d2.dividend_i, d2.divisor_i}

example = Example()
print(verilog.convert(example, example.ios))
5 changes: 2 additions & 3 deletions examples/pytholite/basic.py
Original file line number Diff line number Diff line change
@@ -17,8 +17,7 @@ def run_sim(ng):
g.add_connection(ng, d)

c = CompositeActor(g)
fragment = c.get_fragment()
sim = Simulator(fragment)
sim = Simulator(c)
sim.run(30)
del sim

@@ -32,6 +31,6 @@ def main():
run_sim(ng_pytholite)

print("Converting Pytholite to Verilog:")
print(verilog.convert(ng_pytholite.get_fragment()))
print(verilog.convert(ng_pytholite))

main()
23 changes: 12 additions & 11 deletions examples/pytholite/uio.py
Original file line number Diff line number Diff line change
@@ -7,6 +7,7 @@
from migen.pytholite.transel import Register
from migen.pytholite.compiler import make_pytholite
from migen.sim.generic import Simulator
from migen.fhdl.module import Module
from migen.fhdl.specials import Memory
from migen.fhdl import verilog

@@ -29,18 +30,18 @@ class SlaveModel(wishbone.TargetModel):
def read(self, address):
return address + 4

class TestBench(Module):
def __init__(self, ng):
g = DataFlowGraph()
d = Dumper(layout)
g.add_connection(ng, d)

self.submodules.slave = wishbone.Target(SlaveModel())
self.submodules.intercon = wishbone.InterconnectPointToPoint(ng.buses["wb"], self.slave.bus)
self.submodules.ca = CompositeActor(g)

def run_sim(ng):
g = DataFlowGraph()
d = Dumper(layout)
g.add_connection(ng, d)

slave = wishbone.Target(SlaveModel())
intercon = wishbone.InterconnectPointToPoint(ng.buses["wb"], slave.bus)

c = CompositeActor(g)
fragment = slave.get_fragment() + intercon.get_fragment() + c.get_fragment()

sim = Simulator(fragment)
sim = Simulator(TestBench(ng))
sim.run(50)
del sim

2 changes: 2 additions & 0 deletions migen/fhdl/verilog.py
Original file line number Diff line number Diff line change
@@ -260,6 +260,8 @@ def convert(f, ios=None, name="top",
return_ns=False,
special_overrides=dict(),
display_run=False):
if not isinstance(f, Fragment):
f = f.get_fragment()
if ios is None:
ios = set()
if clock_domains is None:
2 changes: 2 additions & 0 deletions migen/sim/generic.py
Original file line number Diff line number Diff line change
@@ -76,6 +76,8 @@ def get(self, sockaddr):

class Simulator:
def __init__(self, fragment, top_level=None, sim_runner=None, sockaddr="simsocket", **vopts):
if not isinstance(fragment, Fragment):
fragment = fragment.get_fragment()
if top_level is None:
top_level = TopLevel()
if sim_runner is None:
3 changes: 1 addition & 2 deletions vpi/Makefile
Original file line number Diff line number Diff line change
@@ -1,6 +1,5 @@
CC=clang
INSTDIR=/usr/lib/ivl
INCDIRS=
INCDIRS=-I/usr/include/iverilog

OBJ=ipc.o main.o