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base repository: m-labs/migen
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compare: 6fca1dd4dc4f
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  • 3 commits
  • 3 files changed
  • 2 contributors

Commits on Dec 21, 2014

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Showing with 92 additions and 48 deletions.
  1. +13 −6 mibuild/xilinx_vivado.py
  2. +74 −38 migen/actorlib/crc.py
  3. +5 −4 migen/genlib/crc.py
19 changes: 13 additions & 6 deletions mibuild/xilinx_vivado.py
Original file line number Diff line number Diff line change
@@ -41,7 +41,7 @@ def _build_xdc(named_sc, named_pc):
r += "\n" + "\n\n".join(named_pc)
return r

def _build_files(device, sources, vincpaths, build_name, bitstream_compression):
def _build_files(device, sources, vincpaths, build_name, bitstream_commands, additional_commands):
tcl = []
for filename, language in sources:
tcl.append("add_files " + filename.replace("\\", "/"))
@@ -61,9 +61,11 @@ def _build_files(device, sources, vincpaths, build_name, bitstream_compression):
tcl.append("report_drc -file %s_drc.rpt" %(build_name))
tcl.append("report_timing_summary -max_paths 10 -file %s_timing.rpt" %(build_name))
tcl.append("report_power -file %s_power.rpt" %(build_name))
if bitstream_compression:
tcl.append("set_property BITSTREAM.GENERAL.COMPRESS True [current_design]")
for bitstream_command in bitstream_commands:
tcl.append(bitstream_command.format(build_name=build_name))
tcl.append("write_bitstream -force %s.bit " %build_name)
for additional_command in additional_commands:
tcl.append(additional_command.format(build_name=build_name))
tcl.append("quit")
tools.write_to_file(build_name + ".tcl", "\n".join(tcl))

@@ -87,9 +89,13 @@ def _run_vivado(build_name, vivado_path, source, ver=None):
raise OSError("Subprocess failed")

class XilinxVivadoPlatform(xilinx_common.XilinxGenericPlatform):
def __init__(self, *args, **kwargs):
xilinx_common.XilinxGenericPlatform.__init__(self, *args, **kwargs)
self.bitstream_commands = []
self.additional_commands = []

def build(self, fragment, build_dir="build", build_name="top",
vivado_path="/opt/Xilinx/Vivado", source=True, run=True,
bitstream_compression=False):
vivado_path="/opt/Xilinx/Vivado", source=True, run=True):
tools.mkdir_noerror(build_dir)
os.chdir(build_dir)

@@ -100,7 +106,8 @@ def build(self, fragment, build_dir="build", build_name="top",
v_file = build_name + ".v"
tools.write_to_file(v_file, v_src)
sources = self.sources + [(v_file, "verilog")]
_build_files(self.device, sources, self.verilog_include_paths, build_name, bitstream_compression)
_build_files(self.device, sources, self.verilog_include_paths, build_name,
self.bitstream_commands, self.additional_commands)
tools.write_to_file(build_name + ".xdc", _build_xdc(named_sc, named_pc))
if run:
_run_vivado(build_name, vivado_path, source)
112 changes: 74 additions & 38 deletions migen/actorlib/crc.py
Original file line number Diff line number Diff line change
@@ -4,6 +4,7 @@
from migen.genlib.misc import chooser
from migen.genlib.crc import *
from migen.flow.actor import Sink, Source
from migen.actorlib.fifo import SyncFIFO

class CRCInserter(Module):
"""CRC Inserter
@@ -30,44 +31,53 @@ def __init__(self, crc_class, layout):
###

dw = flen(sink.d)
self.submodules.crc = crc_class(dw)
self.submodules.fsm = fsm = FSM(reset_state="IDLE")
crc = crc_class(dw)
fsm = FSM(reset_state="IDLE")
self.submodules += crc, fsm

fsm.act("IDLE",
self.crc.reset.eq(1),
crc.reset.eq(1),
sink.ack.eq(1),
If(sink.stb & sink.sop,
sink.ack.eq(0),
NextState("COPY"),
)
)
fsm.act("COPY",
self.crc.ce.eq(sink.stb & source.ack),
self.crc.d.eq(sink.d),
crc.ce.eq(sink.stb & source.ack),
crc.d.eq(sink.d),
Record.connect(sink, source),
source.eop.eq(0),
If(sink.stb & sink.eop & source.ack,
NextState("INSERT"),
)
)
ratio = self.crc.width//dw
cnt = Signal(max=ratio, reset=ratio-1)
cnt_done = Signal()
fsm.act("INSERT",
source.stb.eq(1),
chooser(self.crc.value, cnt, source.d, reverse=True),
If(cnt_done,
ratio = crc.width//dw
if ratio > 1:
cnt = Signal(max=ratio, reset=ratio-1)
cnt_done = Signal()
fsm.act("INSERT",
source.stb.eq(1),
chooser(crc.value, cnt, source.d, reverse=True),
If(cnt_done,
source.eop.eq(1),
If(source.ack, NextState("IDLE"))
)
)
self.comb += cnt_done.eq(cnt == 0)
self.sync += \
If(fsm.ongoing("IDLE"),
cnt.eq(cnt.reset)
).Elif(fsm.ongoing("INSERT") & ~cnt_done,
cnt.eq(cnt - source.ack)
)
else:
fsm.act("INSERT",
source.stb.eq(1),
source.eop.eq(1),
source.d.eq(crc.value),
If(source.ack, NextState("IDLE"))
)
)
self.comb += cnt_done.eq(cnt == 0)
self.sync += \
If(fsm.ongoing("IDLE"),
cnt.eq(cnt.reset)
).Elif(fsm.ongoing("INSERT") & ~cnt_done,
cnt.eq(cnt - source.ack)
)
self.comb += self.busy.eq(~fsm.ongoing("IDLE"))

class CRC32Inserter(CRCInserter):
@@ -89,7 +99,7 @@ class CRCChecker(Module):
sink : in
Packets input with CRC.
source : out
Packets output with CRC and "error" set to 0
Packets output without CRC and "error" set to 0
on eop when CRC OK / set to 1 when CRC KO.
"""
def __init__(self, crc_class, layout):
@@ -100,32 +110,58 @@ def __init__(self, crc_class, layout):
###

dw = flen(sink.d)
self.submodules.crc = crc_class(dw)
crc = crc_class(dw)
self.submodules += crc
ratio = crc.width//dw

fsm = FSM(reset_state="RESET_CRC")
error = Signal()
fifo = InsertReset(SyncFIFO(layout, ratio + 1))
self.submodules += fifo

fsm = FSM(reset_state="RESET")
self.submodules += fsm

fsm.act("RESET_CRC",
sink.ack.eq(0),
self.crc.reset.eq(1),
NextState("IDLE")
fifo_in = Signal()
fifo_out = Signal()
fifo_full = Signal()

self.comb += [
fifo_full.eq(fifo.fifo.level == ratio),
fifo_in.eq(sink.stb & (~fifo_full | fifo_out)),
fifo_out.eq(source.stb & source.ack),

Record.connect(sink, fifo.sink),
fifo.sink.stb.eq(fifo_in),
self.sink.ack.eq(fifo_in),

source.stb.eq(sink.stb & fifo_full),
source.sop.eq(fifo.source.sop),
source.eop.eq(sink.eop),
fifo.source.ack.eq(fifo_out),
source.payload.eq(fifo.source.payload),

source.error.eq(sink.error | crc.error),
]

fsm.act("RESET",
crc.reset.eq(1),
fifo.reset.eq(1),
NextState("IDLE"),
)
fsm.act("IDLE",
sink.ack.eq(sink.stb),
If(sink.stb & sink.sop,
Record.connect(sink, source),
self.crc.ce.eq(sink.ack),
self.crc.d.eq(sink.d),
crc.d.eq(sink.d),
If(sink.stb & sink.sop & sink.ack,
crc.ce.eq(1),
NextState("COPY")
)
)
fsm.act("COPY",
Record.connect(sink, source),
self.crc.ce.eq(sink.stb & sink.ack),
self.crc.d.eq(sink.d),
source.error.eq(sink.eop & self.crc.error),
If(sink.stb & sink.ack & sink.eop,
NextState("RESET_CRC")
crc.d.eq(sink.d),
If(sink.stb & sink.ack,
crc.ce.eq(1),
If(sink.eop,
NextState("RESET")
)
)
)
self.comb += self.busy.eq(~fsm.ongoing("IDLE"))
9 changes: 5 additions & 4 deletions migen/genlib/crc.py
Original file line number Diff line number Diff line change
@@ -53,11 +53,11 @@ def _optimize_eq(l):
curval = [[("state", i)] for i in range(width)]
for i in range(dat_width):
feedback = curval.pop() + [("din", i)]
curval.insert(0, feedback)
for j in range(1, width-1):
if (polynom&(1<<j)):
for j in range(width-1):
if (polynom & (1<<(j+1))):
curval[j] += feedback
curval[j] = _optimize_eq(curval[j])
curval.insert(0, feedback)

# implement logic
for i in range(width):
@@ -92,6 +92,7 @@ class CRC32(Module):
"""
width = 32
polynom = 0x04C11DB7
init = 2**width-1
check = 0xC704DD7B
def __init__(self, dat_width):
self.d = Signal(dat_width)
@@ -101,7 +102,7 @@ def __init__(self, dat_width):
###

self.submodules.engine = CRCEngine(dat_width, self.width, self.polynom)
reg = Signal(self.width, reset=2**self.width-1)
reg = Signal(self.width, reset=self.init)
self.sync += reg.eq(self.engine.next)
self.comb += [
self.engine.d.eq(self.d),