Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: m-labs/migen
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: 55ab01f928a6
Choose a base ref
...
head repository: m-labs/migen
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: d2cbc70190a7
Choose a head ref
  • 3 commits
  • 3 files changed
  • 1 contributor

Commits on Feb 25, 2013

  1. uio/ioo: fix specials

    Sebastien Bourdeauducq committed Feb 25, 2013
    Copy the full SHA
    425de02 View commit details
  2. fhdl/specials: allow setting memory name

    Sebastien Bourdeauducq committed Feb 25, 2013
    Copy the full SHA
    a81781f View commit details
  3. bank/description: memprefix

    Sebastien Bourdeauducq committed Feb 25, 2013
    Copy the full SHA
    d2cbc70 View commit details
Showing with 8 additions and 4 deletions.
  1. +5 −0 migen/bank/description.py
  2. +2 −3 migen/fhdl/specials.py
  3. +1 −1 migen/uio/ioo.py
5 changes: 5 additions & 0 deletions migen/bank/description.py
Original file line number Diff line number Diff line change
@@ -5,6 +5,11 @@ def regprefix(prefix, registers):
register.name = prefix + register.name
return registers

def memprefix(prefix, memories):
for memory in memories:
memory.name_override = prefix + memory.name_override
return memories

class RegisterRaw:
def __init__(self, name, size=1):
self.name = name
5 changes: 2 additions & 3 deletions migen/fhdl/specials.py
Original file line number Diff line number Diff line change
@@ -180,12 +180,13 @@ def __init__(self, adr, dat_r, we=None, dat_w=None,
self.clock_domain = clock_domain

class Memory(Special):
def __init__(self, width, depth, init=None):
def __init__(self, width, depth, init=None, name="mem"):
Special.__init__(self)
self.width = width
self.depth = depth
self.ports = []
self.init = init
self.name_override = name

def get_port(self, write_capable=False, async_read=False,
has_re=False, we_granularity=0, mode=WRITE_FIRST,
@@ -234,8 +235,6 @@ def add(*sigs):
add(p.dat_r)
return s

name_override = "mem"

@staticmethod
def emit_verilog(memory, ns, clock_domains):
r = ""
2 changes: 1 addition & 1 deletion migen/uio/ioo.py
Original file line number Diff line number Diff line change
@@ -15,7 +15,7 @@ def __init__(self, dataflow=None, buses={}):
self._memories = set(v for v in self.buses.values() if isinstance(v, Memory))

def get_fragment(self):
return Fragment(specials={self._memories})
return Fragment(specials=self._memories)

(_WAIT_COMPLETE, _WAIT_POLL) = range(2)