remove trailing whitespaces

m-labs · Oct 17, 2014 · 53ded72 · 53ded72
1 parent 20528c6
commit 53ded72
Showing 22 changed files with 95 additions and 109 deletions.
diff --git a/make.py b/make.py
@@ -42,7 +42,7 @@ def _get_args():
 	parser.add_argument("-Op", "--platform-option", default=[], nargs=2, action="append", help="set platform-specific option")
 	parser.add_argument("-X", "--external", default="", help="use external directory for targets, platforms and imports")
 	parser.add_argument("--csr_csv", default="csr.csv", help="CSV file to save the CSR map into")
-	
+
 	parser.add_argument("-d", "--decorate", default=[], action="append", help="apply simplification decorator to top-level")
 	parser.add_argument("-Ob", "--build-option", default=[], nargs=2, action="append", help="set build option")
 	parser.add_argument("-f", "--flash-proxy-dir", default=None, help="set search directory for flash proxy bitstreams")

diff --git a/misoclib/dfii/__init__.py b/misoclib/dfii/__init__.py
@@ -10,7 +10,7 @@ def __init__(self, phase):
 		self._baddress = CSRStorage(flen(phase.bank))
 		self._wrdata = CSRStorage(flen(phase.wrdata))
 		self._rddata = CSRStatus(flen(phase.rddata))
-	
+
 		###
 
 		self.comb += [
@@ -39,14 +39,14 @@ def __init__(self, a, ba, d, nphases=1):
 		inti = dfi.Interface(a, ba, d, nphases)
 		self.slave = dfi.Interface(a, ba, d, nphases)
 		self.master = dfi.Interface(a, ba, d, nphases)
-		
+
 		self._control = CSRStorage(4) # sel, cke, odt, reset_n
-		
+
 		for n, phase in enumerate(inti.phases):
 			setattr(self.submodules, "pi" + str(n), PhaseInjector(phase))
-	
+
 		###
-	
+
 		self.comb += If(self._control.storage[0],
 				self.slave.connect(self.master)
 			).Else(

diff --git a/misoclib/framebuffer/__init__.py b/misoclib/framebuffer/__init__.py
@@ -10,7 +10,7 @@
 class Framebuffer(Module, AutoCSR):
 	def __init__(self, pads_vga, pads_dvi, lasmim):
 		pack_factor = lasmim.dw//bpp
-		
+
 		g = DataFlowGraph()
 
 		self.fi = FrameInitiator(lasmim.aw, pack_factor)
@@ -23,7 +23,7 @@ def __init__(self, pads_vga, pads_dvi, lasmim):
 		cast = structuring.Cast(lasmim.dw, pixel_layout(pack_factor), reverse_to=True)
 		vtg = VTG(pack_factor)
 		self.driver = Driver(pack_factor, pads_vga, pads_dvi)
-		
+
 		g.add_connection(self.fi, vtg, source_subr=self.fi.timing_subr, sink_ep="timing")
 		g.add_connection(dma_out, cast)
 		g.add_connection(cast, vtg, sink_ep="pixels")

diff --git a/misoclib/framebuffer/dvi.py b/misoclib/framebuffer/dvi.py
@@ -27,9 +27,9 @@ def __init__(self):
 		self.comb += q_m8_n.eq((n1d > 4) | ((n1d == 4) & ~d[0]))
 		for i in range(8):
 			if i:
-				curval = curval ^ d[i] ^ q_m8_n	
+				curval = curval ^ d[i] ^ q_m8_n
 			else:
-				curval = d[0]		
+				curval = d[0]
 			self.sync += q_m[i].eq(curval)
 		self.sync += q_m[8].eq(~q_m8_n)
 
@@ -199,15 +199,15 @@ def _decode_tmds(b):
 if __name__ == "__main__":
 	from migen.sim.generic import run_simulation
 	from random import Random
-	
+
 	rng = Random(788)
 	test_list = [rng.randrange(256) for i in range(500)]
 	tb = _EncoderTB(test_list)
 	run_simulation(tb)
 
 	check = [_decode_tmds(out)[3] for out in tb.outs]
 	assert(check == test_list)
-	
+
 	nb0 = 0
 	nb1 = 0
 	for out in tb.outs:

diff --git a/misoclib/framebuffer/format.py b/misoclib/framebuffer/format.py
@@ -41,7 +41,7 @@ def __init__(self, bus_aw, pack_factor, ndmas=1):
 			("hsync_start", hbits_dyn, 656, h_alignment_bits),
 			("hsync_end", hbits_dyn, 752, h_alignment_bits),
 			("hscan", hbits_dyn, 800, h_alignment_bits),
-			
+
 			("vres", _vbits, 480),
 			("vsync_start", _vbits, 492),
 			("vsync_end", _vbits, 494),
@@ -81,10 +81,10 @@ def __init__(self, pack_factor):
 		hactive = Signal()
 		vactive = Signal()
 		active = Signal()
-		
+
 		hcounter = Signal(hbits_dyn)
 		vcounter = Signal(_vbits)
-		
+
 		skip = bpc - bpc_phy
 		self.comb += [
 			active.eq(hactive & vactive),
@@ -106,7 +106,7 @@ def __init__(self, pack_factor):
 			generate_frame_done.eq(0),
 			If(generate_en,
 				hcounter.eq(hcounter + 1),
-			
+
 				If(hcounter == 0, hactive.eq(1)),
 				If(hcounter == tr.hres, hactive.eq(0)),
 				If(hcounter == tr.hsync_start, self.phy.payload.hsync.eq(1)),
@@ -120,7 +120,7 @@ def __init__(self, pack_factor):
 						vcounter.eq(vcounter + 1)
 					)
 				),
-				
+
 				If(vcounter == 0, vactive.eq(1)),
 				If(vcounter == tr.vres, vactive.eq(0)),
 				If(vcounter == tr.vsync_start, self.phy.payload.vsync.eq(1)),

diff --git a/misoclib/framebuffer/phy.py b/misoclib/framebuffer/phy.py
@@ -11,14 +11,14 @@ class _FIFO(Module):
 	def __init__(self, pack_factor):
 		self.phy = Sink(phy_layout(pack_factor))
 		self.busy = Signal()
-		
+
 		self.pix_hsync = Signal()
 		self.pix_vsync = Signal()
 		self.pix_de = Signal()
 		self.pix_r = Signal(bpc_phy)
 		self.pix_g = Signal(bpc_phy)
 		self.pix_b = Signal(bpc_phy)
-	
+
 		###
 
 		fifo = RenameClockDomains(AsyncFIFO(phy_layout(pack_factor), 512),
@@ -81,7 +81,7 @@ def __init__(self, pads_vga, pads_dvi):
 		self.specials += Instance("DCM_CLKGEN",
 			p_CLKFXDV_DIVIDE=2, p_CLKFX_DIVIDE=4, p_CLKFX_MD_MAX=1.0, p_CLKFX_MULTIPLY=2,
 			p_CLKIN_PERIOD=20.0, p_SPREAD_SPECTRUM="NONE", p_STARTUP_WAIT="FALSE",
-		
+
 			i_CLKIN=ClockSignal("base50"), o_CLKFX=clk_pix_unbuffered,
 			i_PROGCLK=ClockSignal(), i_PROGDATA=pix_progdata, i_PROGEN=pix_progen,
 			o_PROGDONE=pix_progdone, o_LOCKED=pix_locked,
@@ -145,12 +145,12 @@ def __init__(self, pads_vga, pads_dvi):
 					p_CLKOUT1_DIVIDE=5,  # pix2x
 					p_CLKOUT2_DIVIDE=10, # pix
 					p_COMPENSATION="INTERNAL",
-					
+
 					i_CLKINSEL=1,
 					i_CLKIN1=clk_pix_unbuffered,
 					o_CLKOUT0=pll_clk0, o_CLKOUT1=pll_clk1, o_CLKOUT2=pll_clk2,
 					o_CLKFBOUT=clkfbout, i_CLKFBIN=clkfbout,
-					o_LOCKED=pll_locked, 
+					o_LOCKED=pll_locked,
 					i_RST=~pix_locked | self._r_pll_reset.storage,
 
 					i_DADDR=self._r_pll_adr.storage,

diff --git a/misoclib/gensoc/__init__.py b/misoclib/gensoc/__init__.py
@@ -69,7 +69,7 @@ def __init__(self, platform, clk_freq, cpu_reset_address, sram_size=4096, l2_siz
 
 		# add CPU Verilog sources
 		if cpu_type == "lm32":
-			platform.add_sources(os.path.join("verilog", "lm32", "submodule", "rtl"), 
+			platform.add_sources(os.path.join("verilog", "lm32", "submodule", "rtl"),
 				"lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
 				"lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
 				"lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",

diff --git a/misoclib/identifier/__init__.py b/misoclib/identifier/__init__.py
@@ -9,7 +9,7 @@ def __init__(self, sysid, frequency, l2_size, revision=None):
 		self._r_revision = CSRStatus(32)
 		self._r_frequency = CSRStatus(32)
 		self._r_l2_size = CSRStatus(8)
-		
+
 		###
 
 		if revision is None:

diff --git a/misoclib/lasmicon/__init__.py b/misoclib/lasmicon/__init__.py
@@ -38,7 +38,7 @@ def __init__(self, phy_settings, geom_settings, timing_settings):
 			read_latency=phy_settings.read_latency+1,
 			write_latency=phy_settings.write_latency+1)
 		self.nrowbits = geom_settings.col_a - address_align
-	
+
 		###
 
 		self.submodules.refresher = Refresher(geom_settings.mux_a, geom_settings.bank_a,

diff --git a/misoclib/lasmicon/bankmachine.py b/misoclib/lasmicon/bankmachine.py
@@ -10,21 +10,21 @@ class _AddressSlicer:
 	def __init__(self, col_a, address_align):
 		self.col_a = col_a
 		self.address_align = address_align
-	
+
 	def row(self, address):
 		split = self.col_a - self.address_align
 		if isinstance(address, int):
 			return address >> split
 		else:
 			return address[split:]
-		
+
 	def col(self, address):
 		split = self.col_a - self.address_align
 		if isinstance(address, int):
 			return (address & (2**split - 1)) << self.address_align
 		else:
 			return Cat(Replicate(0, self.address_align), address[:split])
-	
+
 class BankMachine(Module):
 	def __init__(self, geom_settings, timing_settings, address_align, bankn, req):
 		self.refresh_req = Signal()
@@ -47,7 +47,7 @@ def __init__(self, geom_settings, timing_settings, address_align, bankn, req):
 		reqf = self.req_fifo.dout
 
 		slicer = _AddressSlicer(geom_settings.col_a, address_align)
-		
+
 		# Row tracking
 		has_openrow = Signal()
 		openrow = Signal(geom_settings.row_a)
@@ -64,7 +64,7 @@ def __init__(self, geom_settings, timing_settings, address_align, bankn, req):
 				has_openrow.eq(0)
 			)
 		]
-		
+
 		# Address generation
 		s_row_adr = Signal()
 		self.comb += [
@@ -75,7 +75,7 @@ def __init__(self, geom_settings, timing_settings, address_align, bankn, req):
 				self.cmd.a.eq(slicer.col(reqf.adr))
 			)
 		]
-		
+
 		# Respect write-to-precharge specification
 		precharge_ok = Signal()
 		t_unsafe_precharge = 2 + timing_settings.tWR - 1
@@ -88,7 +88,7 @@ def __init__(self, geom_settings, timing_settings, address_align, bankn, req):
 				unsafe_precharge_count.eq(unsafe_precharge_count-1)
 			)
 		]
-		
+
 		# Control and command generation FSM
 		fsm = FSM()
 		self.submodules += fsm

diff --git a/misoclib/lasmicon/multiplexer.py b/misoclib/lasmicon/multiplexer.py
@@ -30,15 +30,15 @@ def __init__(self, requests):
 		self.want_cmds = Signal()
 		# NB: cas_n/ras_n/we_n are 1 when stb is inactive
 		self.cmd = CommandRequestRW(flen(requests[0].a), flen(requests[0].ba))
-	
+
 		###
 
 		rr = RoundRobin(len(requests), SP_CE)
 		self.submodules += rr
-		
+
 		self.comb += [rr.request[i].eq(req.stb & ((req.is_cmd & self.want_cmds) | ((req.is_read == self.want_reads) | (req.is_write == self.want_writes))))
 			for i, req in enumerate(requests)]
-		
+
 		stb = Signal()
 		self.comb += stb.eq(Array(req.stb for req in requests)[rr.grant])
 		for name in ["a", "ba", "is_read", "is_write", "is_cmd"]:
@@ -51,7 +51,7 @@ def __init__(self, requests):
 		self.comb += self.cmd.stb.eq(stb \
 			& ((self.cmd.is_cmd & self.want_cmds) | ((self.cmd.is_read == self.want_reads) \
 			& (self.cmd.is_write == self.want_writes))))
-		
+
 		self.comb += [If(self.cmd.stb & self.cmd.ack & (rr.grant == i), req.ack.eq(1))
 			for i, req in enumerate(requests)]
 		self.comb += rr.ce.eq(self.cmd.ack)
@@ -61,9 +61,9 @@ def __init__(self, commands, dfi):
 		ncmd = len(commands)
 		nph = len(dfi.phases)
 		self.sel = [Signal(max=ncmd) for i in range(nph)]
-	
+
 		###
-	
+
 		def stb_and(cmd, attr):
 			if not hasattr(cmd, "stb"):
 				return 0
@@ -91,7 +91,7 @@ def stb_and(cmd, attr):
 class Multiplexer(Module, AutoCSR):
 	def __init__(self, phy_settings, geom_settings, timing_settings, bank_machines, refresher, dfi, lasmic):
 		assert(phy_settings.nphases == len(dfi.phases))
-	
+
 		# Command choosing
 		requests = [bm.cmd for bm in bank_machines]
 		choose_cmd = _CommandChooser(requests)
@@ -104,24 +104,24 @@ def __init__(self, phy_settings, geom_settings, timing_settings, bank_machines,
 			self.comb += [
 				choose_cmd.want_cmds.eq(1),
 				choose_req.want_cmds.eq(1)
-			]	
+			]
 		self.submodules += choose_cmd, choose_req
-		
+
 		# Command steering
 		nop = CommandRequest(geom_settings.mux_a, geom_settings.bank_a)
 		commands = [nop, choose_cmd.cmd, choose_req.cmd, refresher.cmd] # nop must be 1st
 		(STEER_NOP, STEER_CMD, STEER_REQ, STEER_REFRESH) = range(4)
 		steerer = _Steerer(commands, dfi)
 		self.submodules += steerer
-		
+
 		# Read/write turnaround
 		read_available = Signal()
 		write_available = Signal()
 		self.comb += [
 			read_available.eq(optree("|", [req.stb & req.is_read for req in requests])),
 			write_available.eq(optree("|", [req.stb & req.is_write for req in requests]))
 		]
-		
+
 		def anti_starvation(timeout):
 			en = Signal()
 			max_time = Signal()
@@ -139,12 +139,12 @@ def anti_starvation(timeout):
 			return en, max_time
 		read_time_en, max_read_time = anti_starvation(timing_settings.read_time)
 		write_time_en, max_write_time = anti_starvation(timing_settings.write_time)
-		
+
 		# Refresh
 		self.comb += [bm.refresh_req.eq(refresher.req) for bm in bank_machines]
 		go_to_refresh = Signal()
 		self.comb += go_to_refresh.eq(optree("&", [bm.refresh_gnt for bm in bank_machines]))
-		
+
 		# Datapath
 		all_rddata = [p.rddata for p in dfi.phases]
 		all_wrdata = [p.wrdata for p in dfi.phases]
@@ -154,11 +154,11 @@ def anti_starvation(timeout):
 			Cat(*all_wrdata).eq(lasmic.dat_w),
 			Cat(*all_wrdata_mask).eq(~lasmic.dat_we)
 		]
-		
+
 		# Control FSM
 		fsm = FSM()
 		self.submodules += fsm
-		
+
 		def steerer_sel(steerer, phy_settings, r_w_n):
 			r = []
 			for i in range(phy_settings.nphases):

diff --git a/misoclib/lasmicon/refresher.py b/misoclib/lasmicon/refresher.py
@@ -9,7 +9,7 @@ def __init__(self, a, ba, tRP, tREFI, tRFC):
 		self.req = Signal()
 		self.ack = Signal() # 1st command 1 cycle after assertion of ack
 		self.cmd = CommandRequest(a, ba)
-	
+
 		###
 
 		# Refresh sequence generator:
@@ -37,7 +37,7 @@ def __init__(self, a, ba, tRP, tREFI, tRFC):
 				seq_done.eq(1)
 			])
 		])
-		
+
 		# Periodic refresh counter
 		counter = Signal(max=tREFI)
 		start = Signal()
@@ -50,7 +50,7 @@ def __init__(self, a, ba, tRP, tREFI, tRFC):
 				counter.eq(counter - 1)
 			)
 		]
-		
+
 		# Control FSM
 		fsm = FSM()
 		self.submodules += fsm