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Commit 49cfba5

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author
Sebastien Bourdeauducq
committedFeb 22, 2013
New 'specials' API
·
0.9.20.1
1 parent e82ea19 commit 49cfba5

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18 files changed

+406
-412
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18 files changed

+406
-412
lines changed
 

‎examples/basic/lm32_inst.py

+45-35
Original file line numberDiff line numberDiff line change
@@ -1,50 +1,60 @@
11
from migen.fhdl.structure import *
2+
from migen.fhdl.specials import Instance
3+
from migen.bus import wishbone
24
from migen.fhdl import verilog
35

46
class LM32:
57
def __init__(self):
6-
self.inst = Instance("lm32_top",
8+
self.ibus = i = wishbone.Interface()
9+
self.dbus = d = wishbone.Interface()
10+
self.interrupt = Signal(32)
11+
self.ext_break = Signal()
12+
self._i_adr_o = Signal(32)
13+
self._d_adr_o = Signal(32)
14+
self._inst = Instance("lm32_top",
715
Instance.ClockPort("clk_i"),
816
Instance.ResetPort("rst_i"),
9-
10-
Instance.Input("interrupt", 32),
11-
Instance.Input("ext_break", 1),
12-
13-
Instance.Output("I_ADR_O", 32),
14-
Instance.Output("I_DAT_O", 32),
15-
Instance.Output("I_SEL_O", 4),
16-
Instance.Output("I_CYC_O", 1),
17-
Instance.Output("I_STB_O", 1),
18-
Instance.Output("I_WE_O", 1),
19-
Instance.Output("I_CTI_O", 3),
20-
Instance.Output("I_LOCK_O", 1),
21-
Instance.Output("I_BTE_O", 1),
22-
Instance.Input("I_DAT_I", 32),
23-
Instance.Input("I_ACK_I", 1),
24-
Instance.Input("I_ERR_I", 1),
25-
Instance.Input("I_RTY_I", 1),
2617

27-
Instance.Output("D_ADR_O", 32),
28-
Instance.Output("D_DAT_O", 32),
29-
Instance.Output("D_SEL_O", 4),
30-
Instance.Output("D_CYC_O", 1),
31-
Instance.Output("D_STB_O", 1),
32-
Instance.Output("D_WE_O", 1),
33-
Instance.Output("D_CTI_O", 3),
34-
Instance.Output("D_LOCK_O", 1),
35-
Instance.Output("D_BTE_O", 1),
36-
Instance.Input("D_DAT_I", 32),
37-
Instance.Input("D_ACK_I", 1),
38-
Instance.Input("D_ERR_I", 1),
39-
Instance.Input("D_RTY_I", 1),
18+
Instance.Input("interrupt", self.interrupt),
19+
#Instance.Input("ext_break", self.ext_break),
20+
21+
Instance.Output("I_ADR_O", self._i_adr_o),
22+
Instance.Output("I_DAT_O", i.dat_w),
23+
Instance.Output("I_SEL_O", i.sel),
24+
Instance.Output("I_CYC_O", i.cyc),
25+
Instance.Output("I_STB_O", i.stb),
26+
Instance.Output("I_WE_O", i.we),
27+
Instance.Output("I_CTI_O", i.cti),
28+
Instance.Output("I_LOCK_O"),
29+
Instance.Output("I_BTE_O", i.bte),
30+
Instance.Input("I_DAT_I", i.dat_r),
31+
Instance.Input("I_ACK_I", i.ack),
32+
Instance.Input("I_ERR_I", i.err),
33+
Instance.Input("I_RTY_I", 0),
4034

41-
name="lm32")
42-
35+
Instance.Output("D_ADR_O", self._d_adr_o),
36+
Instance.Output("D_DAT_O", d.dat_w),
37+
Instance.Output("D_SEL_O", d.sel),
38+
Instance.Output("D_CYC_O", d.cyc),
39+
Instance.Output("D_STB_O", d.stb),
40+
Instance.Output("D_WE_O", d.we),
41+
Instance.Output("D_CTI_O", d.cti),
42+
Instance.Output("D_LOCK_O"),
43+
Instance.Output("D_BTE_O", d.bte),
44+
Instance.Input("D_DAT_I", d.dat_r),
45+
Instance.Input("D_ACK_I", d.ack),
46+
Instance.Input("D_ERR_I", d.err),
47+
Instance.Input("D_RTY_I", 0))
48+
4349
def get_fragment(self):
44-
return Fragment(instances=[self.inst])
50+
comb = [
51+
self.ibus.adr.eq(self._i_adr_o[2:]),
52+
self.dbus.adr.eq(self._d_adr_o[2:])
53+
]
54+
return Fragment(comb=comb, specials={self._inst})
4555

4656
cpus = [LM32() for i in range(4)]
4757
frag = Fragment()
4858
for cpu in cpus:
4959
frag += cpu.get_fragment()
50-
print(verilog.convert(frag, set([cpus[0].inst.get_io("interrupt"), cpus[0].inst.get_io("I_WE_O")])))
60+
print(verilog.convert(frag, {cpus[0].interrupt}))

‎examples/basic/memory.py

+3-2
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,12 @@
1-
from migen.fhdl.structure import *
1+
from migen.fhdl.structure import Fragment
2+
from migen.fhdl.specials import Memory
23
from migen.fhdl import verilog
34

45
mem = Memory(32, 100, init=[5, 18, 32])
56
p1 = mem.get_port(write_capable=True, we_granularity=8)
67
p2 = mem.get_port(has_re=True, clock_domain="rd")
78

8-
f = Fragment(memories=[mem])
9+
f = Fragment(specials={mem})
910
v = verilog.convert(f, ios={p1.adr, p1.dat_r, p1.we, p1.dat_w,
1011
p2.adr, p2.dat_r, p2.re})
1112
print(v)

‎examples/basic/tristate.py

+2-1
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,5 @@
11
from migen.fhdl.structure import *
2+
from migen.fhdl.specials import Tristate
23
from migen.fhdl import verilog
34

45
n = 6
@@ -7,5 +8,5 @@
78
oe = Signal()
89
i = Signal(n)
910

10-
f = Fragment(tristates={Tristate(pad, o, oe, i)})
11+
f = Fragment(specials={Tristate(pad, o, oe, i)})
1112
print(verilog.convert(f, ios={pad, o, oe, i}))

‎examples/pytholite/uio.py

+1
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@
77
from migen.pytholite.transel import Register
88
from migen.pytholite.compiler import make_pytholite
99
from migen.sim.generic import Simulator
10+
from migen.fhdl.specials import Memory
1011
from migen.fhdl import verilog
1112

1213
layout = [("r", 32)]

‎examples/sim/memory.py

+2-1
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@
22
# License: GPLv3 with additional permissions (see README).
33

44
from migen.fhdl.structure import *
5+
from migen.fhdl.specials import Memory
56
from migen.sim.generic import Simulator
67

78
class Mem:
@@ -24,7 +25,7 @@ def do_simulation(self, s):
2425
s.interrupt = True
2526

2627
def get_fragment(self):
27-
return Fragment(memories=[self.mem], sim=[self.do_simulation])
28+
return Fragment(specials={self.mem}, sim=[self.do_simulation])
2829

2930
def main():
3031
dut = Mem()

‎migen/actorlib/spi.py

+2-1
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
# Simple Processor Interface
22

33
from migen.fhdl.structure import *
4+
from migen.fhdl.specials import Memory
45
from migen.bank.description import *
56
from migen.flow.actor import *
67

@@ -117,4 +118,4 @@ def get_fragment(self):
117118
self._reg_rd.field.w.eq(rp.dat_r)
118119
]
119120

120-
return Fragment(comb, memories=[mem])
121+
return Fragment(comb, specials={mem})

‎migen/bus/csr.py

+2-1
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,5 @@
11
from migen.fhdl.structure import *
2+
from migen.fhdl.specials import Memory
23
from migen.bus.simple import *
34
from migen.bus.transactions import *
45
from migen.sim.generic import PureSimulable
@@ -97,4 +98,4 @@ def get_fragment(self):
9798
pv = self._page.field.r
9899
comb.append(port.adr.eq(Cat(self.bus.adr[:len(port.adr)-len(pv)], pv)))
99100

100-
return Fragment(comb, sync, memories=[self.mem])
101+
return Fragment(comb, sync, specials={self.mem})

‎migen/bus/wishbone.py

+2-1
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,5 @@
11
from migen.fhdl.structure import *
2+
from migen.fhdl.specials import Memory
23
from migen.corelogic import roundrobin
34
from migen.corelogic.misc import optree
45
from migen.bus.simple import *
@@ -228,4 +229,4 @@ def get_fragment(self):
228229
self.bus.ack.eq(1)
229230
)
230231
]
231-
return Fragment(comb, sync, memories=[self.mem])
232+
return Fragment(comb, sync, specials={self.mem})

‎migen/bus/wishbone2asmi.py

+3-2
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
1-
from migen.bus import wishbone
21
from migen.fhdl.structure import *
2+
from migen.fhdl.specials import Memory
3+
from migen.bus import wishbone
34
from migen.corelogic.fsm import FSM
45
from migen.corelogic.misc import split, displacer, chooser
56
from migen.corelogic.record import Record
@@ -136,5 +137,5 @@ def get_fragment(self):
136137
fsm.next_state(fsm.TEST_HIT)
137138
)
138139

139-
return Fragment(comb, sync, memories=[data_mem, tag_mem]) \
140+
return Fragment(comb, sync, specials={data_mem, tag_mem}) \
140141
+ fsm.get_fragment()

‎migen/fhdl/namer.py

+3-6
Original file line numberDiff line numberDiff line change
@@ -131,13 +131,10 @@ def __init__(self, pnd):
131131
self.pnd = pnd
132132

133133
def get_name(self, sig):
134-
if isinstance(sig, Memory):
135-
sig_name = "mem"
134+
if sig.name_override is not None:
135+
sig_name = sig.name_override
136136
else:
137-
if sig.name_override is not None:
138-
sig_name = sig.name_override
139-
else:
140-
sig_name = self.pnd[sig]
137+
sig_name = self.pnd[sig]
141138
try:
142139
n = self.sigs[sig]
143140
except KeyError:

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