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Sebastien Bourdeauducq
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Feb 22, 2013
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@@ -1,50 +1,60 @@ | ||
from migen.fhdl.structure import * | ||
from migen.fhdl.specials import Instance | ||
from migen.bus import wishbone | ||
from migen.fhdl import verilog | ||
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class LM32: | ||
def __init__(self): | ||
self.inst = Instance("lm32_top", | ||
self.ibus = i = wishbone.Interface() | ||
self.dbus = d = wishbone.Interface() | ||
self.interrupt = Signal(32) | ||
self.ext_break = Signal() | ||
self._i_adr_o = Signal(32) | ||
self._d_adr_o = Signal(32) | ||
self._inst = Instance("lm32_top", | ||
Instance.ClockPort("clk_i"), | ||
Instance.ResetPort("rst_i"), | ||
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Instance.Input("interrupt", 32), | ||
Instance.Input("ext_break", 1), | ||
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Instance.Output("I_ADR_O", 32), | ||
Instance.Output("I_DAT_O", 32), | ||
Instance.Output("I_SEL_O", 4), | ||
Instance.Output("I_CYC_O", 1), | ||
Instance.Output("I_STB_O", 1), | ||
Instance.Output("I_WE_O", 1), | ||
Instance.Output("I_CTI_O", 3), | ||
Instance.Output("I_LOCK_O", 1), | ||
Instance.Output("I_BTE_O", 1), | ||
Instance.Input("I_DAT_I", 32), | ||
Instance.Input("I_ACK_I", 1), | ||
Instance.Input("I_ERR_I", 1), | ||
Instance.Input("I_RTY_I", 1), | ||
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Instance.Output("D_ADR_O", 32), | ||
Instance.Output("D_DAT_O", 32), | ||
Instance.Output("D_SEL_O", 4), | ||
Instance.Output("D_CYC_O", 1), | ||
Instance.Output("D_STB_O", 1), | ||
Instance.Output("D_WE_O", 1), | ||
Instance.Output("D_CTI_O", 3), | ||
Instance.Output("D_LOCK_O", 1), | ||
Instance.Output("D_BTE_O", 1), | ||
Instance.Input("D_DAT_I", 32), | ||
Instance.Input("D_ACK_I", 1), | ||
Instance.Input("D_ERR_I", 1), | ||
Instance.Input("D_RTY_I", 1), | ||
Instance.Input("interrupt", self.interrupt), | ||
#Instance.Input("ext_break", self.ext_break), | ||
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Instance.Output("I_ADR_O", self._i_adr_o), | ||
Instance.Output("I_DAT_O", i.dat_w), | ||
Instance.Output("I_SEL_O", i.sel), | ||
Instance.Output("I_CYC_O", i.cyc), | ||
Instance.Output("I_STB_O", i.stb), | ||
Instance.Output("I_WE_O", i.we), | ||
Instance.Output("I_CTI_O", i.cti), | ||
Instance.Output("I_LOCK_O"), | ||
Instance.Output("I_BTE_O", i.bte), | ||
Instance.Input("I_DAT_I", i.dat_r), | ||
Instance.Input("I_ACK_I", i.ack), | ||
Instance.Input("I_ERR_I", i.err), | ||
Instance.Input("I_RTY_I", 0), | ||
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name="lm32") | ||
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Instance.Output("D_ADR_O", self._d_adr_o), | ||
Instance.Output("D_DAT_O", d.dat_w), | ||
Instance.Output("D_SEL_O", d.sel), | ||
Instance.Output("D_CYC_O", d.cyc), | ||
Instance.Output("D_STB_O", d.stb), | ||
Instance.Output("D_WE_O", d.we), | ||
Instance.Output("D_CTI_O", d.cti), | ||
Instance.Output("D_LOCK_O"), | ||
Instance.Output("D_BTE_O", d.bte), | ||
Instance.Input("D_DAT_I", d.dat_r), | ||
Instance.Input("D_ACK_I", d.ack), | ||
Instance.Input("D_ERR_I", d.err), | ||
Instance.Input("D_RTY_I", 0)) | ||
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def get_fragment(self): | ||
return Fragment(instances=[self.inst]) | ||
comb = [ | ||
self.ibus.adr.eq(self._i_adr_o[2:]), | ||
self.dbus.adr.eq(self._d_adr_o[2:]) | ||
] | ||
return Fragment(comb=comb, specials={self._inst}) | ||
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cpus = [LM32() for i in range(4)] | ||
frag = Fragment() | ||
for cpu in cpus: | ||
frag += cpu.get_fragment() | ||
print(verilog.convert(frag, set([cpus[0].inst.get_io("interrupt"), cpus[0].inst.get_io("I_WE_O")]))) | ||
print(verilog.convert(frag, {cpus[0].interrupt})) |
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Original file line number | Diff line number | Diff line change |
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@@ -1,11 +1,12 @@ | ||
from migen.fhdl.structure import * | ||
from migen.fhdl.structure import Fragment | ||
from migen.fhdl.specials import Memory | ||
from migen.fhdl import verilog | ||
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mem = Memory(32, 100, init=[5, 18, 32]) | ||
p1 = mem.get_port(write_capable=True, we_granularity=8) | ||
p2 = mem.get_port(has_re=True, clock_domain="rd") | ||
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f = Fragment(memories=[mem]) | ||
f = Fragment(specials={mem}) | ||
v = verilog.convert(f, ios={p1.adr, p1.dat_r, p1.we, p1.dat_w, | ||
p2.adr, p2.dat_r, p2.re}) | ||
print(v) |
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