Use RenameClockDomains decorator instead of add_submodule

m-labs · Jul 26, 2013 · bf32559 · bf32559
1 parent 8e04de5
commit bf32559
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Showing 5 changed files with 12 additions and 10 deletions.
diff --git a/milkymist/dvisampler/analysis.py b/milkymist/dvisampler/analysis.py
@@ -137,8 +137,9 @@ def __init__(self):
 			vsync_r.eq(self.vsync)
 		]
 
-		fifo = AsyncFIFO(layout_len(frame_layout), 512)
-		self.add_submodule(fifo, {"write": "pix", "read": "sys"})
+		fifo = RenameClockDomains(AsyncFIFO(layout_len(frame_layout), 512),
+			{"write": "pix", "read": "sys"})
+		self.submodules += fifo
 		self.comb += [
 			fifo.we.eq(fifo_stb),
 			fifo.din.eq(fifo_in.raw_bits()),

diff --git a/milkymist/dvisampler/chansync.py b/milkymist/dvisampler/chansync.py
@@ -56,8 +56,8 @@ def __init__(self, nchan=3, depth=8):
 
 			###
 
-			syncbuffer = _SyncBuffer(layout_len(channel_layout), depth)
-			self.add_submodule(syncbuffer, "pix")
+			syncbuffer = RenameClockDomains(_SyncBuffer(layout_len(channel_layout), depth), "pix")
+			self.submodules += syncbuffer
 			self.comb += [
 				syncbuffer.din.eq(data_in.raw_bits()),
 				data_out.raw_bits().eq(syncbuffer.dout)

diff --git a/milkymist/dvisampler/debug.py b/milkymist/dvisampler/debug.py
@@ -25,8 +25,9 @@ def __init__(self, pads, asmiport):
 			self.data0_cap.serdesstrobe.eq(self.clocking.serdesstrobe)
 		]
 
-		fifo = AsyncFIFO(10, 256)
-		self.add_submodule(fifo, {"write": "pix", "read": "sys"})
+		fifo = RenameClockDomains(AsyncFIFO(10, 256),
+			{"write": "pix", "read": "sys"})
+		self.submodules += fifo
 		self.comb += [
 			fifo.din.eq(self.data0_cap.d),
 			fifo.we.eq(1)

diff --git a/milkymist/framebuffer/lib.py b/milkymist/framebuffer/lib.py
@@ -128,8 +128,9 @@ def __init__(self):
 		###
 
 		data_width = 2+2*3*bpc_dac
-		fifo = AsyncFIFO(data_width, 512)
-		self.add_submodule(fifo, {"write": "sys", "read": "vga"})
+		fifo = RenameClockDomains(AsyncFIFO(data_width, 512),
+			{"write": "sys", "read": "vga"})
+		self.submodules += fifo
 		fifo_in = self.dac.payload
 		fifo_out = Record(dac_layout)
 		self.comb += [

diff --git a/tb/dvisampler/chansync.py b/tb/dvisampler/chansync.py
@@ -7,8 +7,7 @@ class TB(Module):
 	def __init__(self, test_seq_it):
 		self.test_seq_it = test_seq_it
 
-		self.chansync = ChanSync()
-		self.add_submodule(self.chansync, {"pix": "sys"})
+		self.submodules.chansync = RenameClockDomains(ChanSync(), {"pix": "sys"})
 		self.comb += self.chansync.valid_i.eq(1)
 
 	def do_simulation(self, s):