Remove uses of pads, new constraints system

m-labs · Apr 2, 2012 · 19b1cc2 · 19b1cc2
1 parent d2c4afe
commit 19b1cc2
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Showing 6 changed files with 81 additions and 83 deletions.
diff --git a/constraints.py b/constraints.py
@@ -1,69 +1,74 @@
-def get(ns, crg0, norflash0, uart0, ddrphy0):
-	constraints = []
-	def add(signal, pin, vec=-1, iostandard="LVCMOS33", extra=""):
-		constraints.append((ns.get_name(signal), vec, pin, iostandard, extra))
-	def add_vec(signal, pins, iostandard="LVCMOS33", extra=""):
-		assert(signal.bv.width == len(pins))
-		i = 0
-		for p in pins:
-			add(signal, p, i, iostandard, extra)
-			i += 1
-
-	add(crg0.clkin, "AB11", extra="TNM_NET = \"GRPclk50\"")
-	add(crg0.ac97_rst_n, "D6")
-	add(crg0.videoin_rst_n, "W17")
-	add(crg0.flash_rst_n, "P22", extra="SLEW = FAST | DRIVE = 8")
-	add(crg0.trigger_reset, "AA4")
-
-	add_vec(norflash0.adr, ["L22", "L20", "K22", "K21", "J19", "H20", "F22",
-		"F21", "K17", "J17", "E22", "E20", "H18", "H19", "F20",
-		"G19", "C22", "C20", "D22", "D21", "F19", "F18", "D20", "D19"],
-		extra="SLEW = FAST | DRIVE = 8")
-	add_vec(norflash0.d, ["AA20", "U14", "U13", "AA6", "AB6", "W4", "Y4", "Y7",
-		"AA2", "AB2", "V15", "AA18", "AB18", "Y13", "AA12", "AB12"],
-		extra="SLEW = FAST | DRIVE = 8 | PULLDOWN")
-	add(norflash0.oe_n, "M22", extra="SLEW = FAST | DRIVE = 8")
-	add(norflash0.we_n, "N20", extra="SLEW = FAST | DRIVE = 8")
-	add(norflash0.ce_n, "M21", extra="SLEW = FAST | DRIVE = 8")
-
-	add(uart0.tx, "L17", extra="SLEW = SLOW")
-	add(uart0.rx, "K18", extra="PULLUP")
-
-	ddrsettings = "IOSTANDARD = SSTL2_I"
-	add(ddrphy0.sd_clk_out_p, "M3", extra=ddrsettings)
-	add(ddrphy0.sd_clk_out_n, "L4", extra=ddrsettings)
-	add_vec(ddrphy0.sd_a, ["B1", "B2", "H8", "J7", "E4", "D5", "K7", "F5",
-		"G6", "C1", "C3", "D1", "D2"], extra=ddrsettings)
-	add_vec(ddrphy0.sd_ba, ["A2", "E6"], extra=ddrsettings)
-	add(ddrphy0.sd_cs_n, "F7", extra=ddrsettings)
-	add(ddrphy0.sd_cke, "G7", extra=ddrsettings)
-	add(ddrphy0.sd_ras_n, "E5", extra=ddrsettings)
-	add(ddrphy0.sd_cas_n, "C4", extra=ddrsettings)
-	add(ddrphy0.sd_we_n, "D3", extra=ddrsettings)
-	add_vec(ddrphy0.sd_dq, ["Y2", "W3", "W1", "P8", "P7", "P6", "P5", "T4", "T3",
-		"U4", "V3", "N6", "N7", "M7", "M8", "R4", "P4", "M6", "L6", "P3", "N4",
-		"M5", "V2", "V1", "U3", "U1", "T2", "T1", "R3", "R1", "P2", "P1"],
-		extra=ddrsettings)
-	add_vec(ddrphy0.sd_dm, ["E1", "E3", "F3", "G4"], extra=ddrsettings)
-	add_vec(ddrphy0.sd_dqs, ["F1", "F2", "H5", "H6"], extra=ddrsettings)
-
-	r = ""
-	for c in constraints:
-		r += "NET \"" + c[0]
-		if c[1] >= 0:
-			r += "(" + str(c[1]) + ")"
-		r += "\" LOC = " + c[2] 
-		r += " | IOSTANDARD = " + c[3]
-		if c[4]:
-			r += " | " + c[4]
-		r += ";\n"
-
-	r += """
+class Constraints:
+	def __init__(self, crg0, norflash0, uart0, ddrphy0):
+		self.constraints = []
+		def add(signal, pin, vec=-1, iostandard="LVCMOS33", extra=""):
+			self.constraints.append((signal, vec, pin, iostandard, extra))
+		def add_vec(signal, pins, iostandard="LVCMOS33", extra=""):
+			assert(signal.bv.width == len(pins))
+			i = 0
+			for p in pins:
+				add(signal, p, i, iostandard, extra)
+				i += 1
+
+		add(crg0.clkin, "AB11", extra="TNM_NET = \"GRPclk50\"")
+		add(crg0.ac97_rst_n, "D6")
+		add(crg0.videoin_rst_n, "W17")
+		add(crg0.flash_rst_n, "P22", extra="SLEW = FAST | DRIVE = 8")
+		add(crg0.trigger_reset, "AA4")
+
+		add_vec(norflash0.adr, ["L22", "L20", "K22", "K21", "J19", "H20", "F22",
+			"F21", "K17", "J17", "E22", "E20", "H18", "H19", "F20",
+			"G19", "C22", "C20", "D22", "D21", "F19", "F18", "D20", "D19"],
+			extra="SLEW = FAST | DRIVE = 8")
+		add_vec(norflash0.d, ["AA20", "U14", "U13", "AA6", "AB6", "W4", "Y4", "Y7",
+			"AA2", "AB2", "V15", "AA18", "AB18", "Y13", "AA12", "AB12"],
+			extra="SLEW = FAST | DRIVE = 8 | PULLDOWN")
+		add(norflash0.oe_n, "M22", extra="SLEW = FAST | DRIVE = 8")
+		add(norflash0.we_n, "N20", extra="SLEW = FAST | DRIVE = 8")
+		add(norflash0.ce_n, "M21", extra="SLEW = FAST | DRIVE = 8")
+
+		add(uart0.tx, "L17", extra="SLEW = SLOW")
+		add(uart0.rx, "K18", extra="PULLUP")
+
+		ddrsettings = "IOSTANDARD = SSTL2_I"
+		add(ddrphy0.sd_clk_out_p, "M3", extra=ddrsettings)
+		add(ddrphy0.sd_clk_out_n, "L4", extra=ddrsettings)
+		add_vec(ddrphy0.sd_a, ["B1", "B2", "H8", "J7", "E4", "D5", "K7", "F5",
+			"G6", "C1", "C3", "D1", "D2"], extra=ddrsettings)
+		add_vec(ddrphy0.sd_ba, ["A2", "E6"], extra=ddrsettings)
+		add(ddrphy0.sd_cs_n, "F7", extra=ddrsettings)
+		add(ddrphy0.sd_cke, "G7", extra=ddrsettings)
+		add(ddrphy0.sd_ras_n, "E5", extra=ddrsettings)
+		add(ddrphy0.sd_cas_n, "C4", extra=ddrsettings)
+		add(ddrphy0.sd_we_n, "D3", extra=ddrsettings)
+		add_vec(ddrphy0.sd_dq, ["Y2", "W3", "W1", "P8", "P7", "P6", "P5", "T4", "T3",
+			"U4", "V3", "N6", "N7", "M7", "M8", "R4", "P4", "M6", "L6", "P3", "N4",
+			"M5", "V2", "V1", "U3", "U1", "T2", "T1", "R3", "R1", "P2", "P1"],
+			extra=ddrsettings)
+		add_vec(ddrphy0.sd_dm, ["E1", "E3", "F3", "G4"], extra=ddrsettings)
+		add_vec(ddrphy0.sd_dqs, ["F1", "F2", "H5", "H6"], extra=ddrsettings)
+
+	def get_ios(self):
+		return set([c[0] for c in self.constraints])
+
+	def get_ucf(self, ns):
+		r = ""
+		for c in self.constraints:
+			r += "NET \"" + ns.get_name(c[0])
+			if c[1] >= 0:
+				r += "(" + str(c[1]) + ")"
+			r += "\" LOC = " + c[2] 
+			r += " | IOSTANDARD = " + c[3]
+			if c[4]:
+				r += " | " + c[4]
+			r += ";\n"
+
+		r += """
 TIMESPEC "TSclk50" = PERIOD "GRPclk50" 20 ns HIGH 50%;
 INST "m1crg/wr_bufpll" LOC = "BUFPLL_X0Y2";
 INST "m1crg/rd_bufpll" LOC = "BUFPLL_X0Y3";
 
 PIN "m1crg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE;
 """
 
-	return r
+		return r
diff --git a/milkymist/m1crg/__init__.py b/milkymist/m1crg/__init__.py
@@ -41,5 +41,4 @@ def __init__(self, infreq, outfreq1x):
 		)
 
 	def get_fragment(self):
-		return Fragment(instances=[self._inst],
-			pads={self.clkin, self.ac97_rst_n, self.videoin_rst_n, self.flash_rst_n})
+		return Fragment(instances=[self._inst])
diff --git a/milkymist/norflash/__init__.py b/milkymist/norflash/__init__.py
@@ -28,4 +28,4 @@ def get_fragment(self):
 			(2*self.rd_timing + 1, [
 				self.bus.ack.eq(0)])
 		])
-		return Fragment(comb, sync, pads={self.adr, self.d, self.oe_n, self.we_n, self.ce_n})
+		return Fragment(comb, sync)
diff --git a/milkymist/s6ddrphy/__init__.py b/milkymist/s6ddrphy/__init__.py
@@ -7,19 +7,13 @@ def __init__(self, a, ba, d):
 		outs = []
 		inouts = []
 
-		for name in [
-			"clk2x_270",
-			"clk4x_wr",
-			"clk4x_wr_strb",
-			"clk4x_rd",
-			"clk4x_rd_strb"
-		]:
-			s = Signal(name=name)
-			setattr(self, name, s)
-			ins.append((name, s))
-
-		self._sd_pins = []
 		for name, width, l in [
+			("clk2x_270", 1, ins),
+			("clk4x_wr", 1, ins),
+			("clk4x_wr_strb", 1, ins),
+			("clk4x_rd", 1, ins),
+			("clk4x_rd_strb", 1, ins),
+
 			("sd_clk_out_p", 1, outs),
 			("sd_clk_out_n", 1, outs),
 			("sd_a", a, outs),
@@ -37,7 +31,6 @@ def __init__(self, a, ba, d):
 			s = Signal(BV(width), name=name)
 			setattr(self, name, s)
 			l.append((name, s))
-			self._sd_pins.append(s)
 
 		self.dfi = dfi.Interface(a, ba, d, 2)
 		ins += self.dfi.get_standard_names(True, False)
@@ -55,4 +48,4 @@ def __init__(self, a, ba, d):
 			clkport="sys_clk")
 
 	def get_fragment(self):
-		return Fragment(instances=[self._inst], pads=set(self._sd_pins))
+		return Fragment(instances=[self._inst])
diff --git a/milkymist/uart/__init__.py b/milkymist/uart/__init__.py
@@ -107,4 +107,4 @@ def get_fragment(self):
 
 		return self.bank.get_fragment() \
 			+ self.events.get_fragment() \
-			+ Fragment(comb, sync, pads={self.tx, self.rx})
+			+ Fragment(comb, sync)
diff --git a/top.py b/top.py
@@ -6,7 +6,7 @@
 from migen.bus import wishbone, wishbone2asmi, csr, wishbone2csr, dfi
 
 from milkymist import m1crg, lm32, norflash, uart, sram, s6ddrphy, dfii, asmicon
-import constraints
+from constraints import Constraints
 
 MHz = 1000000
 clk_freq = (83 + Fraction(1, 3))*MHz
@@ -122,11 +122,12 @@ def get():
 	crg0 = m1crg.M1CRG(50*MHz, clk_freq)
 
 	frag = autofragment.from_local() + interrupts + ddrphy_clocking(crg0, ddrphy0)
+	cst = Constraints(crg0, norflash0, uart0, ddrphy0)
 	src_verilog, vns = verilog.convert(frag,
-		{crg0.trigger_reset},
+		cst.get_ios(),
 		name="soc",
 		clk_signal=crg0.sys_clk,
 		rst_signal=crg0.sys_rst,
 		return_ns=True)
-	src_ucf = constraints.get(vns, crg0, norflash0, uart0, ddrphy0)
+	src_ucf = cst.get_ucf(vns)
 	return (src_verilog, src_ucf)