fhdl/verilog: fix representation of negative integers

Give the explicit two's complement representation for the given bit width. This results in less readable code compared to using unary minus, but fixes a bug when trying to represent the most negative integer.
m-labs · Dec 11, 2013 · 135a4fe · 135a4fe
1 parent d6cb981
commit 135a4fe
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/migen/fhdl/verilog.py b/migen/fhdl/verilog.py
@@ -27,7 +27,8 @@ def _printintbool(node):
 		if node >= 0:
 			return str(bits_for(node)) + "'d" + str(node), False
 		else:
-			return "-" + str(bits_for(node)) + "'sd" + str(-node), True
+			nbits = bits_for(node)
+			return str(nbits) + "'sd" + str(2**nbits + node), True
 	else:
 		raise TypeError