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Refresh testbenches and convert to new API
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Sebastien Bourdeauducq committed Jan 28, 2014
1 parent e464935 commit 25acf17
Showing 16 changed files with 119 additions and 441 deletions.
41 changes: 41 additions & 0 deletions misoclib/dvisampler/chansync.py
Original file line number Diff line number Diff line change
@@ -86,3 +86,44 @@ def __init__(self, nchan=3, depth=8):
)
)
self.specials += MultiReg(self.chan_synced, self._r_channels_synced.status)

class _TB(Module):
def __init__(self, test_seq_it):
self.test_seq_it = test_seq_it

self.submodules.chansync = RenameClockDomains(ChanSync(), {"pix": "sys"})
self.comb += self.chansync.valid_i.eq(1)

def do_simulation(self, selfp):
try:
de0, de1, de2 = next(self.test_seq_it)
except StopIteration:
raise StopSimulation

selfp.chansync.data_in0.de = de0
selfp.chansync.data_in1.de = de1
selfp.chansync.data_in2.de = de2
selfp.chansync.data_in0.d = selfp.simulator.cycle_counter
selfp.chansync.data_in1.d = selfp.simulator.cycle_counter
selfp.chansync.data_in2.d = selfp.simulator.cycle_counter

out0 = selfp.chansync.data_out0.d
out1 = selfp.chansync.data_out1.d
out2 = selfp.chansync.data_out2.d

print("{0:5} {1:5} {2:5}".format(out0, out1, out2))

if __name__ == "__main__":
from migen.sim.generic import run_simulation

test_seq = [
(1, 1, 1),
(1, 1, 0),
(0, 0, 0),
(0, 0, 0),
(0, 0, 1),
(1, 1, 1),
(1, 1, 1),
]
tb = _TB(iter(test_seq*2))
run_simulation(tb)
18 changes: 9 additions & 9 deletions misoclib/framebuffer/dvi.py
Original file line number Diff line number Diff line change
@@ -164,18 +164,18 @@ def __init__(self, inputs):
self.submodules.dut = Encoder()
self.comb += self.dut.de.eq(1)

def do_simulation(self, s):
def do_simulation(self, selfp):
if self._end_cycle is None:
try:
nv = next(self._iter_inputs)
except StopIteration:
self._end_cycle = s.cycle_counter + 4
self._end_cycle = selfp.simulator.cycle_counter + 4
else:
s.wr(self.dut.d, nv)
if s.cycle_counter == self._end_cycle:
s.interrupt = True
if s.cycle_counter > 4:
self.outs.append(s.rd(self.dut.out))
selfp.dut.d = nv
if selfp.simulator.cycle_counter == self._end_cycle:
raise StopSimulation
if selfp.simulator.cycle_counter > 4:
self.outs.append(selfp.dut.out)

def _bit(i, n):
return (i >> n) & 1
@@ -197,13 +197,13 @@ def _decode_tmds(b):
return de, hsync, vsync, value

if __name__ == "__main__":
from migen.sim.generic import Simulator
from migen.sim.generic import run_simulation
from random import Random

rng = Random(788)
test_list = [rng.randrange(256) for i in range(500)]
tb = _EncoderTB(test_list)
Simulator(tb).run()
run_simulation(tb)

check = [_decode_tmds(out)[3] for out in tb.outs]
assert(check == test_list)
Original file line number Diff line number Diff line change
@@ -1,10 +1,10 @@
from migen.fhdl.std import *
from migen.bus.lasmibus import *
from migen.sim.generic import Simulator, TopLevel
from migen.sim.generic import run_simulation

from misoclib.lasmicon.bankmachine import *

from common import sdram_geom, sdram_timing, CommandLogger
from common import sdram_phy, sdram_geom, sdram_timing, CommandLogger

def my_generator():
for x in range(10):
@@ -15,30 +15,27 @@ def my_generator():
class TB(Module):
def __init__(self):
self.req = Interface(32, 32, 1,
sdram_timing.req_queue_size, sdram_timing.read_latency, sdram_timing.write_latency)
sdram_timing.req_queue_size, sdram_phy.read_latency, sdram_phy.write_latency)
self.submodules.dut = BankMachine(sdram_geom, sdram_timing, 2, 0, self.req)
self.submodules.logger = CommandLogger(self.dut.cmd, True)
self.generator = my_generator()
self.dat_ack_cnt = 0

def do_simulation(self, s):
if s.rd(self.req.dat_ack):
def do_simulation(self, selfp):
if selfp.req.dat_ack:
self.dat_ack_cnt += 1
if s.rd(self.req.req_ack):
if selfp.req.req_ack:
try:
we, adr = next(self.generator)
except StopIteration:
s.wr(self.req.stb, 0)
if not s.rd(self.req.lock):
s.interrupt = True
selfp.req.stb = 0
if not selfp.req.lock:
print("data ack count: {0}".format(self.dat_ack_cnt))
raise StopSimulation
return
s.wr(self.req.adr, adr)
s.wr(self.req.we, we)
s.wr(self.req.stb, 1)
selfp.req.adr = adr
selfp.req.we = we
selfp.req.stb = 1

def main():
sim = Simulator(TB(), TopLevel("my.vcd"))
sim.run()

main()
if __name__ == "__main__":
run_simulation(TB(), vcd_name="my.vcd")
16 changes: 8 additions & 8 deletions tb/lasmicon/common.py → misoclib/lasmicon/test/common.py
Original file line number Diff line number Diff line change
@@ -2,7 +2,6 @@
from math import ceil

from migen.fhdl.std import *
from migen.sim.generic import Proxy

from misoclib import lasmicon

@@ -80,22 +79,23 @@ def __init__(self, cmd, rw=False):
if rw:
self.comb += self.cmd.ack.eq(1)

def do_simulation(self, s):
elts = ["@" + str(s.cycle_counter)]
cmdp = Proxy(s, self.cmd)
def do_simulation(self, selfp):
elts = ["@" + str(selfp.simulator.cycle_counter)]
cmdp = selfp.cmd
elts += decode_sdram(cmdp.ras_n, cmdp.cas_n, cmdp.we_n, cmdp.ba, cmdp.a)
if len(elts) > 1:
print("\t".join(elts))
do_simulation.passive = True

class DFILogger(Module):
def __init__(self, dfi):
self.dfi = dfi

def do_simulation(self, s):
dfip = Proxy(s, self.dfi)

def do_simulation(self, selfp):
dfip = selfp.dfi
for i, p in enumerate(dfip.phases):
elts = ["@" + str(s.cycle_counter) + ":" + str(i)]
elts = ["@" + str(selfp.simulator.cycle_counter) + ":" + str(i)]
elts += decode_sdram(p.ras_n, p.cas_n, p.we_n, p.bank, p.address)
if len(elts) > 1:
print("\t".join(elts))
do_simulation.passive = True
13 changes: 3 additions & 10 deletions tb/lasmicon/lasmicon.py → misoclib/lasmicon/test/lasmicon.py
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
from migen.fhdl.std import *
from migen.bus.lasmibus import *
from migen.sim.generic import Simulator, TopLevel
from migen.sim.generic import run_simulation

from misoclib.lasmicon import *

@@ -35,12 +35,5 @@ def __init__(self):
for n, master in enumerate(masters)]
self.submodules += self.initiators

def do_simulation(self, s):
s.interrupt = all(initiator.done for initiator in self.initiators)


def main():
sim = Simulator(TB(), TopLevel("my.vcd"))
sim.run()

main()
if __name__ == "__main__":
run_simulation(TB(), vcd_name="my.vcd")
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
from migen.fhdl.std import *
from migen.bus import lasmibus
from migen.actorlib import dma_lasmi
from migen.sim.generic import Simulator, TopLevel, Proxy
from migen.sim.generic import run_simulation

from misoclib.lasmicon import *

@@ -11,7 +11,6 @@ class TB(Module):
def __init__(self):
self.submodules.ctler = LASMIcon(sdram_phy, sdram_geom, sdram_timing)
self.submodules.xbar = lasmibus.Crossbar([self.ctler.lasmic], self.ctler.nrowbits)
self.xbar.get_master() # FIXME: remove dummy master
self.submodules.logger = DFILogger(self.ctler.dfi)
self.submodules.writer = dma_lasmi.Writer(self.xbar.get_master())

@@ -25,8 +24,8 @@ def __init__(self):
)
self.open_row = None

def do_simulation(self, s):
dfip = Proxy(s, self.ctler.dfi)
def do_simulation(self, selfp):
dfip = selfp.ctler.dfi
for p in dfip.phases:
if p.ras_n and not p.cas_n and not p.we_n: # write
d = dfip.phases[0].wrdata | (dfip.phases[1].wrdata << 64)
@@ -36,8 +35,5 @@ def do_simulation(self, s):
elif not p.ras_n and p.cas_n and p.we_n: # activate
self.open_row = p.address

def main():
sim = Simulator(TB(), TopLevel("my.vcd"))
sim.run(3500)

main()
if __name__ == "__main__":
run_simulation(TB(), ncycles=3500, vcd_name="my.vcd")
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
from migen.fhdl.std import *
from migen.bus import wishbone, wishbone2lasmi, lasmibus
from migen.bus.transactions import *
from migen.sim.generic import Simulator, TopLevel
from migen.sim.generic import run_simulation

from misoclib.lasmicon import *

@@ -27,17 +27,10 @@ class TB(Module):
def __init__(self):
self.submodules.ctler = LASMIcon(sdram_phy, sdram_geom, sdram_timing)
self.submodules.xbar = lasmibus.Crossbar([self.ctler.lasmic], self.ctler.nrowbits)
self.xbar.get_master() # FIXME: remove dummy master
self.submodules.logger = DFILogger(self.ctler.dfi)
self.submodules.bridge = wishbone2lasmi.WB2LASMI(l2_size//4, self.xbar.get_master())
self.submodules.initiator = wishbone.Initiator(my_generator())
self.submodules.conn = wishbone.InterconnectPointToPoint(self.initiator.bus, self.bridge.wishbone)

def do_simulation(self, s):
s.interrupt = self.initiator.done

def main():
sim = Simulator(TB(), TopLevel("my.vcd"))
sim.run()

main()
if __name__ == "__main__":
run_simulation(TB(), vcd_name="my.vcd")
20 changes: 9 additions & 11 deletions tb/lasmicon/refresher.py → misoclib/lasmicon/test/refresher.py
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
from random import Random

from migen.fhdl.std import *
from migen.sim.generic import Simulator, TopLevel
from migen.sim.generic import run_simulation

from misoclib.lasmicon.refresher import *

@@ -14,22 +14,22 @@ def __init__(self, req, ack):
self.state = 0
self.prng = Random(92837)

def do_simulation(self, s):
elts = ["@" + str(s.cycle_counter)]
def do_simulation(self, selfp):
elts = ["@" + str(selfp.simulator.cycle_counter)]

if self.state == 0:
if s.rd(self.req):
if selfp.req:
elts.append("Refresher requested access")
self.state = 1
elif self.state == 1:
if self.prng.randrange(0, 5) == 0:
elts.append("Granted access to refresher")
s.wr(self.ack, 1)
selfp.ack = 1
self.state = 2
elif self.state == 2:
if not s.rd(self.req):
if not selfp.req:
elts.append("Refresher released access")
s.wr(self.ack, 0)
selfp.ack = 0
self.state = 0

if len(elts) > 1:
@@ -41,7 +41,5 @@ def __init__(self):
self.submodules.logger = CommandLogger(self.dut.cmd)
self.submodules.granter = Granter(self.dut.req, self.dut.ack)

def main():
Simulator(TB()).run(400)

main()
if __name__ == "__main__":
run_simulation(TB(), ncycles=400)
36 changes: 15 additions & 21 deletions misoclib/memtest/__init__.py
Original file line number Diff line number Diff line change
@@ -25,25 +25,6 @@ def __init__(self, n_out, n_state=31, taps=[27, 30]):
self.o.eq(Cat(*curval))
]

def _print_lfsr_code():
from migen.fhdl import verilog
dut = LFSR(3, 4, [3, 2])
print(verilog.convert(dut, ios={dut.ce, dut.reset, dut.o}))

class _LFSRTB(Module):
def __init__(self, *args, **kwargs):
self.submodules.lfsr = LFSR(*args, **kwargs)
self.comb += self.lfsr.ce.eq(1)

def do_simulation(self, s):
print("{0:032x}".format(s.rd(self.lfsr.o)))

def _sim_lfsr():
from migen.sim.generic import Simulator
tb = _LFSRTB(128)
sim = Simulator(tb)
sim.run(20)

memtest_magic = 0x361f

class MemtestWriter(Module):
@@ -113,6 +94,19 @@ def __init__(self, lasmim):
def get_csrs(self):
return [self._r_magic, self._r_reset, self._r_error_count] + self._dma.get_csrs()

class _LFSRTB(Module):
def __init__(self, *args, **kwargs):
self.submodules.dut = LFSR(*args, **kwargs)
self.comb += self.dut.ce.eq(1)

def do_simulation(self, selfp):
print("{0:032x}".format(selfp.dut.o))

if __name__ == "__main__":
_print_lfsr_code()
_sim_lfsr()
from migen.fhdl import verilog
from migen.sim.generic import run_simulation

lfsr = LFSR(3, 4, [3, 2])
print(verilog.convert(lfsr, ios={lfsr.ce, lfsr.reset, lfsr.o}))

run_simulation(_LFSRTB(128), ncycles=20)
26 changes: 8 additions & 18 deletions misoclib/spiflash/__init__.py
Original file line number Diff line number Diff line change
@@ -4,7 +4,6 @@
from migen.genlib.misc import timeline
from migen.genlib.record import Record


class SpiFlash(Module):
def __init__(self, pads, cmd=0xfffefeff, cmd_width=32, addr_width=24,
dummy=15, div=2):
@@ -85,8 +84,6 @@ def __init__(self, pads, cmd=0xfffefeff, cmd_width=32, addr_width=24,

self.sync += timeline(bus.cyc & bus.stb & (i == div - 1), tseq)



class SpiFlashTB(Module):
def __init__(self):
self.submodules.master = wishbone.Initiator(self.gen_reads())
@@ -103,29 +100,22 @@ def gen_reads(self):
yield t
print("read {} in {} cycles(s)".format(t.data, t.latency))

def do_simulation(self, s):
if s.rd(self.pads.cs_n):
def do_simulation(self, selfp):
if selfp.pads.cs_n:
self.cycle = 0
else:
self.cycle += 1
if not s.rd(self.slave.dq.oe):
s.wr(self.slave.dq.i, self.cycle & 0xf)
s.interrupt = self.master.done

if not selfp.slave.dq.oe:
selfp.slave.dq.i = self.cycle & 0xf
do_simulation.passive = True

def _main():
from migen.sim.generic import Simulator, TopLevel
if __name__ == "__main__":
from migen.sim.generic import run_simulation
from migen.fhdl import verilog

pads = Record([("cs_n", 1), ("clk", 1), ("dq", 4)])
s = SpiFlash(pads)
print(verilog.convert(s, ios={pads.clk, pads.cs_n, pads.dq, s.bus.adr,
s.bus.dat_r, s.bus.cyc, s.bus.ack, s.bus.stb}))

tb = SpiFlashTB()
sim = Simulator(tb, TopLevel("spiflash.vcd"))
sim.run()


if __name__ == "__main__":
_main()
run_simulation(SpiFlashTB(), vcd_name="spiflash.vcd")
10 changes: 4 additions & 6 deletions misoclib/videostream/downscaler.py
Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
from migen.fhdl.std import *
from migen.genlib.fsm import *
from migen.sim.generic import run_simulation

class Chopper(Module):
def __init__(self, N, frac_bits):
@@ -104,9 +105,8 @@ class _ChopperTB(Module):
def __init__(self):
self.submodules.dut = Chopper(4, 16)

def gen_simulation(self, s):
from migen.sim.generic import Proxy
dut = Proxy(s, self.dut)
def gen_simulation(self, selfp):
dut = selfp.dut

dut.init = 1
dut.p = 320
@@ -130,6 +130,4 @@ def gen_simulation(self, s):
print("Ones: {} (expected: {})".format(ones, dut.p*niter*4//dut.q))

if __name__ == "__main__":
from migen.sim.generic import Simulator
with Simulator(_ChopperTB()) as s:
s.run(1000)
run_simulation(_ChopperTB())
46 changes: 0 additions & 46 deletions tb/dvisampler/chansync.py

This file was deleted.

37 changes: 0 additions & 37 deletions tb/framebuffer/framebuffer.py

This file was deleted.

25 changes: 0 additions & 25 deletions tb/s6ddrphy/Makefile

This file was deleted.

45 changes: 0 additions & 45 deletions tb/s6ddrphy/gtkwave.sav

This file was deleted.

169 changes: 0 additions & 169 deletions tb/s6ddrphy/tb_s6ddrphy.v

This file was deleted.

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