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Commit 25acf17

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author
Sebastien Bourdeauducq
committedJan 28, 2014
Refresh testbenches and convert to new API
·
0.120.1
1 parent e464935 commit 25acf17

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16 files changed

+119
-441
lines changed

16 files changed

+119
-441
lines changed
 

‎misoclib/dvisampler/chansync.py

+41
Original file line numberDiff line numberDiff line change
@@ -86,3 +86,44 @@ def __init__(self, nchan=3, depth=8):
8686
)
8787
)
8888
self.specials += MultiReg(self.chan_synced, self._r_channels_synced.status)
89+
90+
class _TB(Module):
91+
def __init__(self, test_seq_it):
92+
self.test_seq_it = test_seq_it
93+
94+
self.submodules.chansync = RenameClockDomains(ChanSync(), {"pix": "sys"})
95+
self.comb += self.chansync.valid_i.eq(1)
96+
97+
def do_simulation(self, selfp):
98+
try:
99+
de0, de1, de2 = next(self.test_seq_it)
100+
except StopIteration:
101+
raise StopSimulation
102+
103+
selfp.chansync.data_in0.de = de0
104+
selfp.chansync.data_in1.de = de1
105+
selfp.chansync.data_in2.de = de2
106+
selfp.chansync.data_in0.d = selfp.simulator.cycle_counter
107+
selfp.chansync.data_in1.d = selfp.simulator.cycle_counter
108+
selfp.chansync.data_in2.d = selfp.simulator.cycle_counter
109+
110+
out0 = selfp.chansync.data_out0.d
111+
out1 = selfp.chansync.data_out1.d
112+
out2 = selfp.chansync.data_out2.d
113+
114+
print("{0:5} {1:5} {2:5}".format(out0, out1, out2))
115+
116+
if __name__ == "__main__":
117+
from migen.sim.generic import run_simulation
118+
119+
test_seq = [
120+
(1, 1, 1),
121+
(1, 1, 0),
122+
(0, 0, 0),
123+
(0, 0, 0),
124+
(0, 0, 1),
125+
(1, 1, 1),
126+
(1, 1, 1),
127+
]
128+
tb = _TB(iter(test_seq*2))
129+
run_simulation(tb)

‎misoclib/framebuffer/dvi.py

+9-9
Original file line numberDiff line numberDiff line change
@@ -164,18 +164,18 @@ def __init__(self, inputs):
164164
self.submodules.dut = Encoder()
165165
self.comb += self.dut.de.eq(1)
166166

167-
def do_simulation(self, s):
167+
def do_simulation(self, selfp):
168168
if self._end_cycle is None:
169169
try:
170170
nv = next(self._iter_inputs)
171171
except StopIteration:
172-
self._end_cycle = s.cycle_counter + 4
172+
self._end_cycle = selfp.simulator.cycle_counter + 4
173173
else:
174-
s.wr(self.dut.d, nv)
175-
if s.cycle_counter == self._end_cycle:
176-
s.interrupt = True
177-
if s.cycle_counter > 4:
178-
self.outs.append(s.rd(self.dut.out))
174+
selfp.dut.d = nv
175+
if selfp.simulator.cycle_counter == self._end_cycle:
176+
raise StopSimulation
177+
if selfp.simulator.cycle_counter > 4:
178+
self.outs.append(selfp.dut.out)
179179

180180
def _bit(i, n):
181181
return (i >> n) & 1
@@ -197,13 +197,13 @@ def _decode_tmds(b):
197197
return de, hsync, vsync, value
198198

199199
if __name__ == "__main__":
200-
from migen.sim.generic import Simulator
200+
from migen.sim.generic import run_simulation
201201
from random import Random
202202

203203
rng = Random(788)
204204
test_list = [rng.randrange(256) for i in range(500)]
205205
tb = _EncoderTB(test_list)
206-
Simulator(tb).run()
206+
run_simulation(tb)
207207

208208
check = [_decode_tmds(out)[3] for out in tb.outs]
209209
assert(check == test_list)

‎tb/lasmicon/bankmachine.py ‎misoclib/lasmicon/test/bankmachine.py

+14-17
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,10 @@
11
from migen.fhdl.std import *
22
from migen.bus.lasmibus import *
3-
from migen.sim.generic import Simulator, TopLevel
3+
from migen.sim.generic import run_simulation
44

55
from misoclib.lasmicon.bankmachine import *
66

7-
from common import sdram_geom, sdram_timing, CommandLogger
7+
from common import sdram_phy, sdram_geom, sdram_timing, CommandLogger
88

99
def my_generator():
1010
for x in range(10):
@@ -15,30 +15,27 @@ def my_generator():
1515
class TB(Module):
1616
def __init__(self):
1717
self.req = Interface(32, 32, 1,
18-
sdram_timing.req_queue_size, sdram_timing.read_latency, sdram_timing.write_latency)
18+
sdram_timing.req_queue_size, sdram_phy.read_latency, sdram_phy.write_latency)
1919
self.submodules.dut = BankMachine(sdram_geom, sdram_timing, 2, 0, self.req)
2020
self.submodules.logger = CommandLogger(self.dut.cmd, True)
2121
self.generator = my_generator()
2222
self.dat_ack_cnt = 0
2323

24-
def do_simulation(self, s):
25-
if s.rd(self.req.dat_ack):
24+
def do_simulation(self, selfp):
25+
if selfp.req.dat_ack:
2626
self.dat_ack_cnt += 1
27-
if s.rd(self.req.req_ack):
27+
if selfp.req.req_ack:
2828
try:
2929
we, adr = next(self.generator)
3030
except StopIteration:
31-
s.wr(self.req.stb, 0)
32-
if not s.rd(self.req.lock):
33-
s.interrupt = True
31+
selfp.req.stb = 0
32+
if not selfp.req.lock:
3433
print("data ack count: {0}".format(self.dat_ack_cnt))
34+
raise StopSimulation
3535
return
36-
s.wr(self.req.adr, adr)
37-
s.wr(self.req.we, we)
38-
s.wr(self.req.stb, 1)
36+
selfp.req.adr = adr
37+
selfp.req.we = we
38+
selfp.req.stb = 1
3939

40-
def main():
41-
sim = Simulator(TB(), TopLevel("my.vcd"))
42-
sim.run()
43-
44-
main()
40+
if __name__ == "__main__":
41+
run_simulation(TB(), vcd_name="my.vcd")

‎tb/lasmicon/common.py ‎misoclib/lasmicon/test/common.py

+8-8
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,6 @@
22
from math import ceil
33

44
from migen.fhdl.std import *
5-
from migen.sim.generic import Proxy
65

76
from misoclib import lasmicon
87

@@ -80,22 +79,23 @@ def __init__(self, cmd, rw=False):
8079
if rw:
8180
self.comb += self.cmd.ack.eq(1)
8281

83-
def do_simulation(self, s):
84-
elts = ["@" + str(s.cycle_counter)]
85-
cmdp = Proxy(s, self.cmd)
82+
def do_simulation(self, selfp):
83+
elts = ["@" + str(selfp.simulator.cycle_counter)]
84+
cmdp = selfp.cmd
8685
elts += decode_sdram(cmdp.ras_n, cmdp.cas_n, cmdp.we_n, cmdp.ba, cmdp.a)
8786
if len(elts) > 1:
8887
print("\t".join(elts))
88+
do_simulation.passive = True
8989

9090
class DFILogger(Module):
9191
def __init__(self, dfi):
9292
self.dfi = dfi
9393

94-
def do_simulation(self, s):
95-
dfip = Proxy(s, self.dfi)
96-
94+
def do_simulation(self, selfp):
95+
dfip = selfp.dfi
9796
for i, p in enumerate(dfip.phases):
98-
elts = ["@" + str(s.cycle_counter) + ":" + str(i)]
97+
elts = ["@" + str(selfp.simulator.cycle_counter) + ":" + str(i)]
9998
elts += decode_sdram(p.ras_n, p.cas_n, p.we_n, p.bank, p.address)
10099
if len(elts) > 1:
101100
print("\t".join(elts))
101+
do_simulation.passive = True

‎tb/lasmicon/lasmicon.py ‎misoclib/lasmicon/test/lasmicon.py

+3-10
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
from migen.fhdl.std import *
22
from migen.bus.lasmibus import *
3-
from migen.sim.generic import Simulator, TopLevel
3+
from migen.sim.generic import run_simulation
44

55
from misoclib.lasmicon import *
66

@@ -35,12 +35,5 @@ def __init__(self):
3535
for n, master in enumerate(masters)]
3636
self.submodules += self.initiators
3737

38-
def do_simulation(self, s):
39-
s.interrupt = all(initiator.done for initiator in self.initiators)
40-
41-
42-
def main():
43-
sim = Simulator(TB(), TopLevel("my.vcd"))
44-
sim.run()
45-
46-
main()
38+
if __name__ == "__main__":
39+
run_simulation(TB(), vcd_name="my.vcd")

‎tb/lasmicon/lasmicon_df.py ‎misoclib/lasmicon/test/lasmicon_df.py

+5-9
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
from migen.fhdl.std import *
22
from migen.bus import lasmibus
33
from migen.actorlib import dma_lasmi
4-
from migen.sim.generic import Simulator, TopLevel, Proxy
4+
from migen.sim.generic import run_simulation
55

66
from misoclib.lasmicon import *
77

@@ -11,7 +11,6 @@ class TB(Module):
1111
def __init__(self):
1212
self.submodules.ctler = LASMIcon(sdram_phy, sdram_geom, sdram_timing)
1313
self.submodules.xbar = lasmibus.Crossbar([self.ctler.lasmic], self.ctler.nrowbits)
14-
self.xbar.get_master() # FIXME: remove dummy master
1514
self.submodules.logger = DFILogger(self.ctler.dfi)
1615
self.submodules.writer = dma_lasmi.Writer(self.xbar.get_master())
1716

@@ -25,8 +24,8 @@ def __init__(self):
2524
)
2625
self.open_row = None
2726

28-
def do_simulation(self, s):
29-
dfip = Proxy(s, self.ctler.dfi)
27+
def do_simulation(self, selfp):
28+
dfip = selfp.ctler.dfi
3029
for p in dfip.phases:
3130
if p.ras_n and not p.cas_n and not p.we_n: # write
3231
d = dfip.phases[0].wrdata | (dfip.phases[1].wrdata << 64)
@@ -36,8 +35,5 @@ def do_simulation(self, s):
3635
elif not p.ras_n and p.cas_n and p.we_n: # activate
3736
self.open_row = p.address
3837

39-
def main():
40-
sim = Simulator(TB(), TopLevel("my.vcd"))
41-
sim.run(3500)
42-
43-
main()
38+
if __name__ == "__main__":
39+
run_simulation(TB(), ncycles=3500, vcd_name="my.vcd")

‎tb/lasmicon/lasmicon_wb.py ‎misoclib/lasmicon/test/lasmicon_wb.py

+3-10
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
from migen.fhdl.std import *
22
from migen.bus import wishbone, wishbone2lasmi, lasmibus
33
from migen.bus.transactions import *
4-
from migen.sim.generic import Simulator, TopLevel
4+
from migen.sim.generic import run_simulation
55

66
from misoclib.lasmicon import *
77

@@ -27,17 +27,10 @@ class TB(Module):
2727
def __init__(self):
2828
self.submodules.ctler = LASMIcon(sdram_phy, sdram_geom, sdram_timing)
2929
self.submodules.xbar = lasmibus.Crossbar([self.ctler.lasmic], self.ctler.nrowbits)
30-
self.xbar.get_master() # FIXME: remove dummy master
3130
self.submodules.logger = DFILogger(self.ctler.dfi)
3231
self.submodules.bridge = wishbone2lasmi.WB2LASMI(l2_size//4, self.xbar.get_master())
3332
self.submodules.initiator = wishbone.Initiator(my_generator())
3433
self.submodules.conn = wishbone.InterconnectPointToPoint(self.initiator.bus, self.bridge.wishbone)
3534

36-
def do_simulation(self, s):
37-
s.interrupt = self.initiator.done
38-
39-
def main():
40-
sim = Simulator(TB(), TopLevel("my.vcd"))
41-
sim.run()
42-
43-
main()
35+
if __name__ == "__main__":
36+
run_simulation(TB(), vcd_name="my.vcd")

‎tb/lasmicon/refresher.py ‎misoclib/lasmicon/test/refresher.py

+9-11
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
from random import Random
22

33
from migen.fhdl.std import *
4-
from migen.sim.generic import Simulator, TopLevel
4+
from migen.sim.generic import run_simulation
55

66
from misoclib.lasmicon.refresher import *
77

@@ -14,22 +14,22 @@ def __init__(self, req, ack):
1414
self.state = 0
1515
self.prng = Random(92837)
1616

17-
def do_simulation(self, s):
18-
elts = ["@" + str(s.cycle_counter)]
17+
def do_simulation(self, selfp):
18+
elts = ["@" + str(selfp.simulator.cycle_counter)]
1919

2020
if self.state == 0:
21-
if s.rd(self.req):
21+
if selfp.req:
2222
elts.append("Refresher requested access")
2323
self.state = 1
2424
elif self.state == 1:
2525
if self.prng.randrange(0, 5) == 0:
2626
elts.append("Granted access to refresher")
27-
s.wr(self.ack, 1)
27+
selfp.ack = 1
2828
self.state = 2
2929
elif self.state == 2:
30-
if not s.rd(self.req):
30+
if not selfp.req:
3131
elts.append("Refresher released access")
32-
s.wr(self.ack, 0)
32+
selfp.ack = 0
3333
self.state = 0
3434

3535
if len(elts) > 1:
@@ -41,7 +41,5 @@ def __init__(self):
4141
self.submodules.logger = CommandLogger(self.dut.cmd)
4242
self.submodules.granter = Granter(self.dut.req, self.dut.ack)
4343

44-
def main():
45-
Simulator(TB()).run(400)
46-
47-
main()
44+
if __name__ == "__main__":
45+
run_simulation(TB(), ncycles=400)

‎misoclib/memtest/__init__.py

+15-21
Original file line numberDiff line numberDiff line change
@@ -25,25 +25,6 @@ def __init__(self, n_out, n_state=31, taps=[27, 30]):
2525
self.o.eq(Cat(*curval))
2626
]
2727

28-
def _print_lfsr_code():
29-
from migen.fhdl import verilog
30-
dut = LFSR(3, 4, [3, 2])
31-
print(verilog.convert(dut, ios={dut.ce, dut.reset, dut.o}))
32-
33-
class _LFSRTB(Module):
34-
def __init__(self, *args, **kwargs):
35-
self.submodules.lfsr = LFSR(*args, **kwargs)
36-
self.comb += self.lfsr.ce.eq(1)
37-
38-
def do_simulation(self, s):
39-
print("{0:032x}".format(s.rd(self.lfsr.o)))
40-
41-
def _sim_lfsr():
42-
from migen.sim.generic import Simulator
43-
tb = _LFSRTB(128)
44-
sim = Simulator(tb)
45-
sim.run(20)
46-
4728
memtest_magic = 0x361f
4829

4930
class MemtestWriter(Module):
@@ -113,6 +94,19 @@ def __init__(self, lasmim):
11394
def get_csrs(self):
11495
return [self._r_magic, self._r_reset, self._r_error_count] + self._dma.get_csrs()
11596

97+
class _LFSRTB(Module):
98+
def __init__(self, *args, **kwargs):
99+
self.submodules.dut = LFSR(*args, **kwargs)
100+
self.comb += self.dut.ce.eq(1)
101+
102+
def do_simulation(self, selfp):
103+
print("{0:032x}".format(selfp.dut.o))
104+
116105
if __name__ == "__main__":
117-
_print_lfsr_code()
118-
_sim_lfsr()
106+
from migen.fhdl import verilog
107+
from migen.sim.generic import run_simulation
108+
109+
lfsr = LFSR(3, 4, [3, 2])
110+
print(verilog.convert(lfsr, ios={lfsr.ce, lfsr.reset, lfsr.o}))
111+
112+
run_simulation(_LFSRTB(128), ncycles=20)

‎misoclib/spiflash/__init__.py

+8-18
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,6 @@
44
from migen.genlib.misc import timeline
55
from migen.genlib.record import Record
66

7-
87
class SpiFlash(Module):
98
def __init__(self, pads, cmd=0xfffefeff, cmd_width=32, addr_width=24,
109
dummy=15, div=2):
@@ -85,8 +84,6 @@ def __init__(self, pads, cmd=0xfffefeff, cmd_width=32, addr_width=24,
8584

8685
self.sync += timeline(bus.cyc & bus.stb & (i == div - 1), tseq)
8786

88-
89-
9087
class SpiFlashTB(Module):
9188
def __init__(self):
9289
self.submodules.master = wishbone.Initiator(self.gen_reads())
@@ -103,29 +100,22 @@ def gen_reads(self):
103100
yield t
104101
print("read {} in {} cycles(s)".format(t.data, t.latency))
105102

106-
def do_simulation(self, s):
107-
if s.rd(self.pads.cs_n):
103+
def do_simulation(self, selfp):
104+
if selfp.pads.cs_n:
108105
self.cycle = 0
109106
else:
110107
self.cycle += 1
111-
if not s.rd(self.slave.dq.oe):
112-
s.wr(self.slave.dq.i, self.cycle & 0xf)
113-
s.interrupt = self.master.done
114-
108+
if not selfp.slave.dq.oe:
109+
selfp.slave.dq.i = self.cycle & 0xf
110+
do_simulation.passive = True
115111

116-
def _main():
117-
from migen.sim.generic import Simulator, TopLevel
112+
if __name__ == "__main__":
113+
from migen.sim.generic import run_simulation
118114
from migen.fhdl import verilog
119115

120116
pads = Record([("cs_n", 1), ("clk", 1), ("dq", 4)])
121117
s = SpiFlash(pads)
122118
print(verilog.convert(s, ios={pads.clk, pads.cs_n, pads.dq, s.bus.adr,
123119
s.bus.dat_r, s.bus.cyc, s.bus.ack, s.bus.stb}))
124120

125-
tb = SpiFlashTB()
126-
sim = Simulator(tb, TopLevel("spiflash.vcd"))
127-
sim.run()
128-
129-
130-
if __name__ == "__main__":
131-
_main()
121+
run_simulation(SpiFlashTB(), vcd_name="spiflash.vcd")

‎misoclib/videostream/downscaler.py

+4-6
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
from migen.fhdl.std import *
22
from migen.genlib.fsm import *
3+
from migen.sim.generic import run_simulation
34

45
class Chopper(Module):
56
def __init__(self, N, frac_bits):
@@ -104,9 +105,8 @@ class _ChopperTB(Module):
104105
def __init__(self):
105106
self.submodules.dut = Chopper(4, 16)
106107

107-
def gen_simulation(self, s):
108-
from migen.sim.generic import Proxy
109-
dut = Proxy(s, self.dut)
108+
def gen_simulation(self, selfp):
109+
dut = selfp.dut
110110

111111
dut.init = 1
112112
dut.p = 320
@@ -130,6 +130,4 @@ def gen_simulation(self, s):
130130
print("Ones: {} (expected: {})".format(ones, dut.p*niter*4//dut.q))
131131

132132
if __name__ == "__main__":
133-
from migen.sim.generic import Simulator
134-
with Simulator(_ChopperTB()) as s:
135-
s.run(1000)
133+
run_simulation(_ChopperTB())

‎tb/dvisampler/chansync.py

-46
This file was deleted.

‎tb/framebuffer/framebuffer.py

-37
This file was deleted.

‎tb/s6ddrphy/Makefile

-25
This file was deleted.

‎tb/s6ddrphy/gtkwave.sav

-45
This file was deleted.

‎tb/s6ddrphy/tb_s6ddrphy.v

-169
This file was deleted.

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