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gensdrphy: fix memtype and change phase shift in comments.
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enjoy-digital authored and sbourdeauducq committed May 16, 2014
1 parent 6298624 commit 54339a6
Showing 1 changed file with 2 additions and 2 deletions.
4 changes: 2 additions & 2 deletions misoclib/sdramphy/gensdrphy.py
Original file line number Diff line number Diff line change
@@ -7,7 +7,7 @@
# The PHY needs 2 Clock domains:
# - sys_clk : The System Clock domain
# - sys_clk_ps : The System Clock domain with its phase shifted
# (-0.75ns on C4@100MHz)
# (-3ns on C4@100MHz)
#
# Assert dfi_wrdata_en and present the data
# on dfi_wrdata_mask/dfi_wrdata in the same
@@ -35,7 +35,7 @@ def __init__(self, pads):
d = flen(pads.dq)

self.phy_settings = lasmicon.PhySettings(
memtype=memtype,
memtype="SDR",
dfi_d=d,
nphases=1,
rdphase=0,

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