gensdrphy: fix memtype and change phase shift in comments.

m-labs · May 16, 2014 · 54339a6 · 54339a6
1 parent 6298624
commit 54339a6
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/misoclib/sdramphy/gensdrphy.py b/misoclib/sdramphy/gensdrphy.py
@@ -7,7 +7,7 @@
 # The PHY needs 2 Clock domains:
 #  - sys_clk    : The System Clock domain
 #  - sys_clk_ps : The System Clock domain with its phase shifted 
-#                 (-0.75ns on C4@100MHz)
+#                 (-3ns on C4@100MHz)
 #
 # Assert dfi_wrdata_en and present the data 
 # on dfi_wrdata_mask/dfi_wrdata in the same
@@ -35,7 +35,7 @@ def __init__(self, pads):
 		d = flen(pads.dq)
 
 		self.phy_settings = lasmicon.PhySettings(
-			memtype=memtype,
+			memtype="SDR",
 			dfi_d=d,
 			nphases=1,
 			rdphase=0,