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Sebastien Bourdeauducq
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Feb 11, 2013
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Original file line number | Diff line number | Diff line change |
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#!/usr/bin/env python3 | ||
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import os | ||
from mibuild.platforms import m1 | ||
import top | ||
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# list Verilog sources before changing directory | ||
verilog_sources = [] | ||
def add_core_dir(d): | ||
root = os.path.join("verilog", d) | ||
files = os.listdir(root) | ||
for f in files: | ||
if f[-2:] == ".v": | ||
verilog_sources.append(os.path.join(root, f)) | ||
def add_core_files(d, files): | ||
for f in files: | ||
verilog_sources.append(os.path.join("verilog", d, f)) | ||
add_core_dir("generic") | ||
add_core_dir("m1crg") | ||
add_core_dir("s6ddrphy") | ||
add_core_files("lm32", ["lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v", | ||
"lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v", | ||
"lm32_shifter.v", "lm32_multiplier_spartan6.v", "lm32_mc_arithmetic.v", | ||
"lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v", | ||
"lm32_dcache.v", "lm32_top.v", "lm32_debug.v", "lm32_jtag.v", "jtag_cores.v", | ||
"jtag_tap_spartan6.v"]) | ||
add_core_dir("minimac3") | ||
def main(): | ||
plat = m1.Platform() | ||
soc = top.SoC() | ||
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# set pin constraints | ||
plat.request("clk50", obj=soc.crg.clk50_pad) | ||
plat.request("user_btn", 1, obj=soc.crg.trigger_reset) | ||
plat.request("norflash_rst_n", obj=soc.crg.norflash_rst_n) | ||
plat.request("vga_clock", obj=soc.crg.vga_clk_pad) | ||
plat.request("ddram_clock", obj=soc.crg, name_map=lambda s: "ddr_clk_pad_" + s) | ||
plat.request("eth_clocks", obj=soc.crg, name_map=lambda s: "eth_" + s + "_clk_pad") | ||
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plat.request("norflash", obj=soc.norflash) | ||
plat.request("serial", obj=soc.uart) | ||
plat.request("ddram", obj=soc.ddrphy, name_map=lambda s: "sd_" + s) | ||
plat.request("eth", obj=soc.minimac, name_map=lambda s: "phy_" + s) | ||
plat.request("vga", obj=soc.fb, name_map=lambda s: "vga_" + s) | ||
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# set extra constraints | ||
plat.add_platform_command(""" | ||
NET "{clk50}" TNM_NET = "GRPclk50"; | ||
TIMESPEC "TSclk50" = PERIOD "GRPclk50" 20 ns HIGH 50%; | ||
INST "m1crg/wr_bufpll" LOC = "BUFPLL_X0Y2"; | ||
INST "m1crg/rd_bufpll" LOC = "BUFPLL_X0Y3"; | ||
os.chdir("build") | ||
PIN "m1crg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE; | ||
def str2file(filename, contents): | ||
f = open(filename, "w") | ||
f.write(contents) | ||
f.close() | ||
NET "{phy_rx_clk}" TNM_NET = "GRPphy_rx_clk"; | ||
NET "{phy_tx_clk}" TNM_NET = "GRPphy_tx_clk"; | ||
TIMESPEC "TSphy_rx_clk" = PERIOD "GRPphy_rx_clk" 40 ns HIGH 50%; | ||
TIMESPEC "TSphy_tx_clk" = PERIOD "GRPphy_tx_clk" 40 ns HIGH 50%; | ||
TIMESPEC "TSphy_tx_clk_io" = FROM "GRPphy_tx_clk" TO "PADS" 10 ns; | ||
TIMESPEC "TSphy_rx_clk_io" = FROM "PADS" TO "GRPphy_rx_clk" 10 ns; | ||
# generate source | ||
(src_verilog, src_ucf) = top.get() | ||
str2file("soc.v", src_verilog) | ||
str2file("soc.ucf", src_ucf) | ||
verilog_sources.append("build/soc.v") | ||
NET "asfifo*/counter_read/gray_count*" TIG; | ||
NET "asfifo*/counter_write/gray_count*" TIG; | ||
NET "asfifo*/preset_empty*" TIG; | ||
""", | ||
clk50=soc.crg.clk50_pad, | ||
phy_rx_clk=soc.crg.eth_rx_clk_pad, | ||
phy_tx_clk=soc.crg.eth_tx_clk_pad) | ||
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# add Verilog sources | ||
for d in ["generic", "m1crg", "s6ddrphy", "minimac3"]: | ||
plat.add_source_dir(os.path.join("verilog", d)) | ||
plat.add_sources(os.path.join("verilog", "lm32"), | ||
"lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v", | ||
"lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v", | ||
"lm32_shifter.v", "lm32_multiplier_spartan6.v", "lm32_mc_arithmetic.v", | ||
"lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v", | ||
"lm32_dcache.v", "lm32_top.v", "lm32_debug.v", "lm32_jtag.v", "jtag_cores.v", | ||
"jtag_tap_spartan6.v") | ||
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plat.build_cmdline(soc.get_fragment(), clock_domains=soc.crg.get_clock_domains()) | ||
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# generate XST project file | ||
xst_prj = "" | ||
for s in verilog_sources: | ||
xst_prj += "verilog work ../" + s + "\n" | ||
str2file("soc.prj", xst_prj) | ||
if __name__ == "__main__": | ||
main() |
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