m-labs · Sep 26, 2014 · Sep 26, 2014
Showing with 47 additions and 4 deletions.

+8 −4 README

+39 −0 targets/simple.py
diff --git a/README b/README
@@ -12,11 +12,14 @@ a high performance and small footprint SoC based on Migen
  * mor1kx (a better OpenRISC implementation) as alternative CPU option.
  * High performance memory controller capable of issuing several SDRAM commands
    per FPGA cycle.
- * Supports SDR, DDR, LPDDR and DDR2.
+ * Supports SDR, DDR, LPDDR, DDR2 and DDR3.
  * Provided peripherals: UART, GPIO, timer, GPIO, NOR flash controller, SPI
    flash controller, Ethernet MAC, and more.
- * High performance: on Spartan-6, 83MHz system clock frequencies, 10+Gbps DDR
+ * High performance:
+   - on Spartan-6, 83MHz system clock frequencies, 10+Gbps DDR
    SDRAM bandwidth, 1080p 32bpp framebuffer, etc.
+   - on Kintex-7, 125MHz system clock frequencies (up to 200MHz without DDR3),
+   64Gbps DDR3 SDRAM bandwidth.
  * Low resource usage: basic implementation fits easily in Spartan-6 LX9.
  * Portable and easy to customize thanks to Python- and Migen-based
    architecture.
@@ -46,21 +49,22 @@ modules.
   For Mixxeo and M1: https://github.com/m-labs/fjmem-m1
   For Papilio Pro:   https://github.com/GadgetFactory/Papilio-Loader
     (xc3sprog/trunk/bscan_spi/bscan_spi_lx9_papilio.bit)
+  For KC705: https://github.com/m-labs/bscan_spi_kc705
 
 4. Compile and install binutils. Take the latest version from GNU.
   mkdir build && cd build
   ../configure --target=lm32-elf
   make
   make install
-  
+
 5. Compile and install GCC. Take gcc-core and gcc-g++ from GNU (version 4.5 or >=4.9).
   rm -rf libstdc++-v3
   mkdir build && cd build
   ../configure --target=lm32-elf --enable-languages="c,c++" --disable-libgcc --disable-libssp
   make
   make install
 
-6. Obtain compiler-rt and set the CRTDIR environment variable to the root of 
+6. Obtain compiler-rt and set the CRTDIR environment variable to the root of
   its source tree.
   svn co http://llvm.org/svn/llvm-project/compiler-rt/trunk compiler-rt
   export CRTDIR=/path_to/compiler-rt

diff --git a/targets/simple.py b/targets/simple.py
@@ -0,0 +1,39 @@
+from migen.fhdl.std import *
+from migen.bus import wishbone
+
+from misoclib.gensoc import GenSoC, IntegratedBIOS
+
+class _CRG(Module):
+	def __init__(self, clk_in):
+		self.clock_domains.cd_sys = ClockDomain()
+		self.clock_domains.cd_por = ClockDomain(reset_less=True)
+
+		# Power on Reset (vendor agnostic)
+		rst_n = Signal()
+		self.sync.por += rst_n.eq(1)
+		self.comb += [
+			self.cd_sys.clk.eq(clk_in),
+			self.cd_por.clk.eq(clk_in),
+			self.cd_sys.rst.eq(~rst_n)
+		]
+
+class SimpleSoC(GenSoC, IntegratedBIOS):
+	default_platform = "de0nano"	# /!\ Adapt this!
+	clk_name = "clk50"				# /!\ Adapt this!
+	clk_freq = 50*1000000			# /!\ Adapt this!
+
+	def __init__(self, platform):
+		GenSoC.__init__(self, platform,
+			clk_freq=self.clk_freq,
+			cpu_reset_address=0)
+		IntegratedBIOS.__init__(self)
+
+		self.submodules.crg = _CRG(platform.request(self.clk_name))
+
+		# use on-board SRAM as SDRAM
+		sys_ram_size = 16*1024
+		self.submodules.sys_ram = wishbone.SRAM(sys_ram_size)
+		self.add_wb_slave(lambda a: a[27:29] == 2, self.sys_ram.bus)
+		self.add_cpu_memory_region("sdram", 0x40000000, sys_ram_size)
+
+default_subtarget = SimpleSoC